From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mark Rutland <mark.rutland@arm.com>
Subject: Re: A question about TTBRs
Date: Fri, 24 Feb 2017 12:10:21 +0000
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To: Christoffer Dall <cdall@linaro.org>, Raz <raziebe@gmail.com>
Cc: kvmarm@lists.cs.columbia.edu
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On Fri, Feb 24, 2017 at 11:22:40AM +0100, Christoffer Dall wrote:
> On Fri, Feb 24, 2017 at 09:55:09AM +0000, Raz wrote:
> > Hello
> > I am reading the arm8a book. According to the documentation the output
> > address of each level 3 entry in TTBRx_EL1points to an address in the
> > physical memory.
> > By looking in the mmu tab in the DS5 studio I can see the TTBRs tables.
> > 
> > What I do not understand is why while I have 2GB of RAM in the FVP (
> > /proc/meminfo ) some page entries ( level 3 ) of the ttbr points to memory
> > above 4GB; for instance:
> > 
> > Output address NP:0xF794D000
> > 
> > Doesn't the physical memory starts at address zero ? if not, where its
> > starting point is configured?
> 
> It depends on your particular system where RAM starts, and it does not
> necessarily start at zero.  You'd have to check the documentation of
> your model or hardware or look at the device tree you use, for example.

It's also worth bearing in mind that memory is not necessarily
physically contiguous. There may be several banks with gaps in the
middle, as is the case on ARM Juno systems [1]:

	memory@80000000 {
		device_type = "memory";
		/* last 16MB of the first memory area is reserved for secure world use by firmware */
		reg = <0x00000000 0x80000000 0x0 0x7f000000>,
		      <0x00000008 0x80000000 0x1 0x80000000>;
	};

It may also be the case that MMIO devices fall within these gaps.

Thanks,
Mark.

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/arm/juno-base.dtsi?h=v4.10&id=c470abd4fde40ea6a0846a2beab642a578c0b8cd