From: James Morse <james.morse@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Jonathan.Zhang@cavium.com, Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Dongjiu Geng <gengdongjiu@huawei.com>,
kvmarm@lists.cs.columbia.edu
Subject: [PATCH v5 09/13] KVM: arm64: Save/Restore guest DISR_EL1
Date: Fri, 15 Dec 2017 15:50:57 +0000 [thread overview]
Message-ID: <20171215155101.23505-10-james.morse@arm.com> (raw)
In-Reply-To: <20171215155101.23505-1-james.morse@arm.com>
If we deliver a virtual SError to the guest, the guest may defer it
with an ESB instruction. The guest reads the deferred value via DISR_EL1,
but the guests view of DISR_EL1 is re-mapped to VDISR_EL2 when HCR_EL2.AMO
is set.
Add the KVM code to save/restore VDISR_EL2, and make it accessible to
userspace as DISR_EL1.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/sysreg.h | 1 +
arch/arm64/kvm/hyp/sysreg-sr.c | 6 ++++++
arch/arm64/kvm/sys_regs.c | 1 +
4 files changed, 9 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index c626c081ce9a..9391a076de58 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -121,6 +121,7 @@ enum vcpu_sysreg {
PAR_EL1, /* Physical Address Register */
MDSCR_EL1, /* Monitor Debug System Control Register */
MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
+ DISR_EL1, /* Deferred Interrupt Status Register */
/* Performance Monitors Registers */
PMCR_EL0, /* Control Register */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6afbf2334763..1e5228024c7b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -358,6 +358,7 @@
#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
+#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
index 934137647837..f4d604803b29 100644
--- a/arch/arm64/kvm/hyp/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/sysreg-sr.c
@@ -66,6 +66,9 @@ static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
ctxt->gp_regs.sp_el1 = read_sysreg(sp_el1);
ctxt->gp_regs.elr_el1 = read_sysreg_el1(elr);
ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(spsr);
+
+ if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
+ ctxt->sys_regs[DISR_EL1] = read_sysreg_s(SYS_VDISR_EL2);
}
static hyp_alternate_select(__sysreg_call_save_host_state,
@@ -119,6 +122,9 @@ static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
write_sysreg(ctxt->gp_regs.sp_el1, sp_el1);
write_sysreg_el1(ctxt->gp_regs.elr_el1, elr);
write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],spsr);
+
+ if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
+ write_sysreg_s(ctxt->sys_regs[DISR_EL1], SYS_VDISR_EL2);
}
static hyp_alternate_select(__sysreg_call_restore_host_state,
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1830ebc227d1..9edf4ac8a320 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1169,6 +1169,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
{ SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
+ { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
{ SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
{ SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
--
2.15.0
next prev parent reply other threads:[~2017-12-15 15:50 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-15 15:50 [PATCH v5 00/13] arm64/KVM: RAS & IESB for firmware first support James Morse
2017-12-15 15:50 ` [PATCH v5 01/13] arm64: cpufeature: __this_cpu_has_cap() shouldn't stop early James Morse
2017-12-15 16:24 ` Suzuki K Poulose
2017-12-15 15:50 ` [PATCH v5 02/13] arm64: sysreg: Move to use definitions for all the SCTLR bits James Morse
2017-12-15 15:50 ` [PATCH v5 03/13] arm64: cpufeature: Detect CPU RAS Extentions James Morse
2017-12-15 15:50 ` [PATCH v5 04/13] arm64: kernel: Survive corrected RAS errors notified by SError James Morse
2017-12-16 2:53 ` gengdongjiu
2018-01-05 18:28 ` James Morse
2017-12-16 4:08 ` gengdongjiu
2017-12-16 4:51 ` gengdongjiu
2018-01-05 18:28 ` James Morse
2017-12-15 15:50 ` [PATCH v5 05/13] arm64: Unconditionally enable IESB on exception entry/return for firmware-first James Morse
2017-12-15 15:50 ` [PATCH v5 06/13] arm64: kernel: Prepare for a DISR user James Morse
2017-12-15 15:50 ` [PATCH v5 07/13] KVM: arm/arm64: mask/unmask daif around VHE guests James Morse
2018-01-08 16:26 ` James Morse
2017-12-15 15:50 ` [PATCH v5 08/13] KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2 James Morse
2017-12-15 15:50 ` James Morse [this message]
2017-12-15 15:50 ` [PATCH v5 10/13] KVM: arm64: Save ESR_EL2 on guest SError James Morse
2017-12-15 15:50 ` [PATCH v5 11/13] KVM: arm64: Handle RAS SErrors from EL1 on guest exit James Morse
2017-12-15 15:51 ` [PATCH v5 12/13] KVM: arm64: Handle RAS SErrors from EL2 " James Morse
2017-12-15 15:51 ` [PATCH v5 13/13] KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA James Morse
2018-01-08 16:27 ` James Morse
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