From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBCC7C0650E for ; Thu, 4 Jul 2019 09:01:30 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 6646E218A3 for ; Thu, 4 Jul 2019 09:01:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6646E218A3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D4EAE4A1FA; Thu, 4 Jul 2019 05:01:29 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xKcTWvnVC4-r; Thu, 4 Jul 2019 05:01:24 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 86AD94A32E; Thu, 4 Jul 2019 05:01:24 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B08784A1FA for ; Thu, 4 Jul 2019 05:01:23 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iT1F7taI6gLp for ; Thu, 4 Jul 2019 05:01:22 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 2F4AB40217 for ; Thu, 4 Jul 2019 05:01:22 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 876A3344; Thu, 4 Jul 2019 02:01:21 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2FE073F703; Thu, 4 Jul 2019 02:01:20 -0700 (PDT) Date: Thu, 4 Jul 2019 10:01:17 +0100 From: Andre Przywara To: Julien Thierry Subject: Re: [PATCH 52/59] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Message-ID: <20190704100117.7bba090b@donnerap.cambridge.arm.com> In-Reply-To: <23223923-125c-4d9b-eee9-071a4cf3de2a@arm.com> References: <20190621093843.220980-1-marc.zyngier@arm.com> <20190621093843.220980-53-marc.zyngier@arm.com> <23223923-125c-4d9b-eee9-071a4cf3de2a@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Cc: kvm@vger.kernel.org, Marc Zyngier , kvmarm@lists.cs.columbia.edu, Dave Martin , linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, 4 Jul 2019 08:38:20 +0100 Julien Thierry wrote: > On 21/06/2019 10:38, Marc Zyngier wrote: > > From: Andre Przywara > > > > The VGIC maintenance IRQ signals various conditions about the LRs, when > > the GIC's virtualization extension is used. > > So far we didn't need it, but nested virtualization needs to know about > > this interrupt, so add a userland interface to setup the IRQ number. > > The architecture mandates that it must be a PPI, on top of that this code > > only exports a per-device option, so the PPI is the same on all VCPUs. > > > > Signed-off-by: Andre Przywara > > [added some bits of documentation] > > Signed-off-by: Marc Zyngier > > --- > > .../virtual/kvm/devices/arm-vgic-v3.txt | 9 ++++++++ > > arch/arm/include/uapi/asm/kvm.h | 1 + > > arch/arm64/include/uapi/asm/kvm.h | 1 + > > include/kvm/arm_vgic.h | 3 +++ > > virt/kvm/arm/vgic/vgic-kvm-device.c | 22 +++++++++++++++++++ > > 5 files changed, 36 insertions(+) > > > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > index ff290b43c8e5..c70e8f2e0c9c 100644 > > --- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > +++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > @@ -249,3 +249,12 @@ Groups: > > Errors: > > -EINVAL: vINTID is not multiple of 32 or > > info field is not VGIC_LEVEL_INFO_LINE_LEVEL > > + > > + KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ > > + The attr field of kvm_device_attr encodes the following values: > > + bits: | 31 .... 5 | 4 .... 0 | > > + values: | RES0 | vINTID | > > + > > + The vINTID specifies which interrupt is generated when the vGIC > > + must generate a maintenance interrupt. This must be a PPI. > > + > > Something seems off. The documentation suggests that the value of the > attribute will be between 0-15 (and other values will be masked down to > a value between 0 and 15). Where does that happen? The mask is [4:0], so 5 bits, that should be enough for PPIs as well. We could add a line to the documentation to stress that this is an interrupt ID as seen by the virtual GIC, if that helps. Cheers, Andre. > However, in the code the value should be > between 16 and 32 (PPI INTID) and other values are rejected. > > Am I reading this wrong? > > Cheers, > > Julien > > > diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h > > index 4602464ebdfb..a6af45645a6d 100644 > > --- a/arch/arm/include/uapi/asm/kvm.h > > +++ b/arch/arm/include/uapi/asm/kvm.h > > @@ -233,6 +233,7 @@ struct kvm_vcpu_events { > > #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 > > #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 > > #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 > > +#define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9 > > #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 > > #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ > > (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) > > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > > index 563e2a8bae93..8e1c6ffe1b59 100644 > > --- a/arch/arm64/include/uapi/asm/kvm.h > > +++ b/arch/arm64/include/uapi/asm/kvm.h > > @@ -295,6 +295,7 @@ struct kvm_vcpu_events { > > #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 > > #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 > > #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 > > +#define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9 > > #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 > > #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ > > (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) > > diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h > > index 17d32c2797c0..95c6232663c3 100644 > > --- a/include/kvm/arm_vgic.h > > +++ b/include/kvm/arm_vgic.h > > @@ -229,6 +229,9 @@ struct vgic_dist { > > > > int nr_spis; > > > > + /* The GIC maintenance IRQ for nested hypervisors. */ > > + u32 maint_irq; > > + > > /* base addresses in guest physical address space: */ > > gpa_t vgic_dist_base; /* distributor */ > > union { > > diff --git a/virt/kvm/arm/vgic/vgic-kvm-device.c b/virt/kvm/arm/vgic/vgic-kvm-device.c > > index 44419679f91a..dfb1d7cc66b3 100644 > > --- a/virt/kvm/arm/vgic/vgic-kvm-device.c > > +++ b/virt/kvm/arm/vgic/vgic-kvm-device.c > > @@ -241,6 +241,12 @@ static int vgic_get_common_attr(struct kvm_device *dev, > > VGIC_NR_PRIVATE_IRQS, uaddr); > > break; > > } > > + case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: { > > + u32 __user *uaddr = (u32 __user *)(long)attr->addr; > > + > > + r = put_user(dev->kvm->arch.vgic.maint_irq, uaddr); > > + break; > > + } > > } > > > > return r; > > @@ -627,6 +633,21 @@ static int vgic_v3_set_attr(struct kvm_device *dev, > > reg = tmp32; > > return vgic_v3_attr_regs_access(dev, attr, ®, true); > > } > > + case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: { > > + u32 __user *uaddr = (u32 __user *)(long)attr->addr; > > + u32 val; > > + > > + if (get_user(val, uaddr)) > > + return -EFAULT; > > + > > + /* Must be a PPI. */ > > + if ((val >= VGIC_NR_PRIVATE_IRQS) || (val < VGIC_NR_SGIS)) > > + return -EINVAL; > > + > > + dev->kvm->arch.vgic.maint_irq = val; > > + > > + return 0; > > + } > > case KVM_DEV_ARM_VGIC_GRP_CTRL: { > > int ret; > > > > @@ -712,6 +733,7 @@ static int vgic_v3_has_attr(struct kvm_device *dev, > > case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: > > return vgic_v3_has_attr_regs(dev, attr); > > case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: > > + case KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ: > > return 0; > > case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: { > > if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >> > > > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm