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[34.244.242.0]) by smtp.gmail.com with ESMTPSA id c12sm2671980wro.96.2019.11.22.06.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2019 06:24:25 -0800 (PST) Date: Fri, 22 Nov 2019 15:24:27 +0100 From: "Edgar E. Iglesias" To: Marc Zyngier Subject: Re: [PATCH] target/arm: Fix ISR_EL1 tracking when executing at EL2 Message-ID: <20191122142427.GA29312@toto> References: <20191122135833.28953-1-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191122135833.28953-1-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-Mailman-Approved-At: Fri, 22 Nov 2019 09:30:49 -0500 Cc: Will Deacon , qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Fri, Nov 22, 2019 at 01:58:33PM +0000, Marc Zyngier wrote: > The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1, > ISR_EL1 shows the pending status of the physical IRQ, FIQ, or > SError interrupts. > > Unfortunately, QEMU's implementation only considers the HCR_EL2 > bits, and ignores the current exception level. This means a hypervisor > trying to look at its own interrupt state actually sees the guest > state, which is unexpected and breaks KVM as of Linux 5.3. > > Instead, check for the running EL and return the physical bits > if not running in a virtualized context. > > Fixes: 636540e9c40b > Reported-by: Quentin Perret > Signed-off-by: Marc Zyngier Looks good to me: Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index a089fb5a69..027fffbff6 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -1934,8 +1934,11 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) > CPUState *cs = env_cpu(env); > uint64_t hcr_el2 = arm_hcr_el2_eff(env); > uint64_t ret = 0; > + bool allow_virt = (arm_current_el(env) == 1 && > + (!arm_is_secure_below_el3(env) || > + (env->cp15.scr_el3 & SCR_EEL2))); > > - if (hcr_el2 & HCR_IMO) { > + if (allow_virt && (hcr_el2 & HCR_IMO)) { > if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { > ret |= CPSR_I; > } > @@ -1945,7 +1948,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) > } > } > > - if (hcr_el2 & HCR_FMO) { > + if (allow_virt && (hcr_el2 & HCR_FMO)) { > if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { > ret |= CPSR_F; > } > -- > 2.17.1 > > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm