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Sat, 28 Mar 2020 11:23:55 +0000 Date: Sat, 28 Mar 2020 11:23:51 +0000 From: Marc Zyngier To: Will Deacon Subject: Re: [RFC PATCH] arm64: unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE} Message-ID: <20200328112351.53f800ed@why> In-Reply-To: <20200327180913.GA10454@willie-the-truck> References: <20200327143941.195626-1-ascull@google.com> <1705907b-234c-6f56-1360-f598c8047d1d@arm.com> <20200327174838.GD178422@google.com> <20200327180913.GA10454@willie-the-truck> Organization: Approximate X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: will@kernel.org, ascull@google.com, steven.price@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, qperret@google.com, dbrazdil@google.com, qwandor@google.com, tabba@google.com, wedsonaf@google.com, kernel-team@android.com, James.Morse@arm.com, Suzuki.Poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: qwandor@google.com, tabba@google.com, Steven Price , wedsonaf@google.com, dbrazdil@google.com, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Fri, 27 Mar 2020 18:09:14 +0000 Will Deacon wrote: > On Fri, Mar 27, 2020 at 05:52:59PM +0000, Marc Zyngier wrote: > > On 2020-03-27 17:48, Andrew Scull wrote: > > > Thanks, Steven. Could we look into the EPD* caching microarch details > > > Marc was referring to for these A55 and A76 cores? > > > > Only the folks that have access to the RTL can tell you, unfortunately. > > > > Thankfully, there is a bunch of people on Cc that should be able to ping > > the relevant teams and report back... > > Yup, otherwise I guess we can throw in the TLB invalidation after setting > the EPDx bits until we have clarity from Arm. We wouldn't need to broadcast > it, so it might not be too bad on performance. If it is, I suppose we could > switch to a reserved VMID? I'd like to avoid the reserved VMID if at all possible -- we already have one for the host on nVHE, and I bet your patches are going to create some interesting havoc^Wchanges in that area, as the host is now a guest from the mm perspective. It isn't clear either whether a reserved VMID really solves the problem either, as you could still end-up with speculative PTWs. Can it be harmful to create conflicting TLB entries if you never hit them? But if we bring in TLB invalidation, I wonder whether the problem can be mitigated solely with just that on the affected CPUs, and what the impact would be. /me eyes the D05 running its 32 guests... M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm