From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 488ACC2BA19 for ; Sat, 4 Apr 2020 14:38:46 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 0167D206F5 for ; Sat, 4 Apr 2020 14:38:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="cexJCPH1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0167D206F5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B0C354B1A9; Sat, 4 Apr 2020 10:38:45 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@redhat.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cL1LZnKLNxZ4; Sat, 4 Apr 2020 10:38:44 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6A67D4B15A; Sat, 4 Apr 2020 10:38:44 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A31B44B1A9 for ; Sat, 4 Apr 2020 10:38:43 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MuhBCGzU0WHY for ; Sat, 4 Apr 2020 10:38:42 -0400 (EDT) Received: from us-smtp-delivery-1.mimecast.com (us-smtp-1.mimecast.com [205.139.110.61]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 7B73B4B15A for ; Sat, 4 Apr 2020 10:38:42 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1586011122; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=P9r8K0aGXwOyP5v44zWWM1tcSvLg5nKErcwCi4vPNbw=; b=cexJCPH1Ig8/qnqz3nWduCPKq9iGi2eExKNfhNZuuonDINDFywehHVjH17bgj5RMxuSvjP iJpgzqCSRFADxUHTOe8eInw+h83TwjXl1NFZS1c42OVFEArDroSilZ6O9krMrN8dddky1I A/MoGPi4Ze3vX4G8iafUNmxCo6h9pqw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-492-TjO25IhqPs65ne43NIXDFg-1; Sat, 04 Apr 2020 10:38:40 -0400 X-MC-Unique: TjO25IhqPs65ne43NIXDFg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 23B4018AB2C0; Sat, 4 Apr 2020 14:38:39 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.40.192.30]) by smtp.corp.redhat.com (Postfix) with ESMTP id E7FB19B912; Sat, 4 Apr 2020 14:38:34 +0000 (UTC) From: Andrew Jones To: pbonzini@redhat.com Subject: [PULL kvm-unit-tests 24/39] arm: pmu: test 32-bit <-> 64-bit transitions Date: Sat, 4 Apr 2020 16:37:16 +0200 Message-Id: <20200404143731.208138-25-drjones@redhat.com> In-Reply-To: <20200404143731.208138-1-drjones@redhat.com> References: <20200404143731.208138-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu From: Eric Auger Test configurations where we transit from 32b to 64b counters and conversely. Also tests configuration where chain counters are configured but only one counter is enabled. Signed-off-by: Eric Auger Signed-off-by: Andrew Jones --- arm/pmu.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++ 2 files changed, 144 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 73e55498284d..9602e70f4185 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -57,6 +57,7 @@ #define ALL_SET 0xFFFFFFFF #define ALL_CLEAR 0x0 #define PRE_OVERFLOW 0xFFFFFFF0 +#define PRE_OVERFLOW2 0xFFFFFFDC struct pmu { unsigned int version; @@ -144,6 +145,7 @@ static void test_mem_access(void) {} static void test_sw_incr(void) {} static void test_chained_counters(void) {} static void test_chained_sw_incr(void) {} +static void test_chain_promotion(void) {} #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -594,6 +596,138 @@ static void test_chained_sw_incr(void) read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); } +static void test_chain_promotion(void) +{ + uint32_t events[] = {MEM_ACCESS, CHAIN}; + void *addr = malloc(PAGE_SIZE); + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + /* Only enable CHAIN counter */ + pmu_reset(); + write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x2, PMCNTENSET_EL0); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(!read_regn_el0(pmevcntr, 0), + "chain counter not counting if even counter is disabled"); + + /* Only enable even counter */ + pmu_reset(); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); + write_sysreg_s(0x1, PMCNTENSET_EL0); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1), + "odd counter did not increment on overflow if disabled"); + report_info("MEM_ACCESS counter #0 has value %ld", + read_regn_el0(pmevcntr, 0)); + report_info("CHAIN counter #1 has value %ld", + read_regn_el0(pmevcntr, 1)); + report_info("overflow counter %ld", read_sysreg(pmovsclr_el0)); + + /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled */ + pmu_reset(); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + /* disable the CHAIN event */ + write_sysreg_s(0x2, PMCNTENCLR_EL0); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + report(read_sysreg(pmovsclr_el0) == 0x1, + "should have triggered an overflow on #0"); + report(!read_regn_el0(pmevcntr, 1), + "CHAIN counter #1 shouldn't have incremented"); + + /* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled */ + + pmu_reset(); + write_sysreg_s(0x1, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + isb(); + report_info("counter #0 = 0x%lx, counter #1 = 0x%lx overflow=0x%lx", + read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), + read_sysreg(pmovsclr_el0)); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + /* enable the CHAIN event */ + write_sysreg_s(0x3, PMCNTENSET_EL0); + isb(); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), + "CHAIN counter enabled: CHAIN counter was incremented and no overflow"); + + report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", + read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + + /* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */ + pmu_reset(); + write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + /* 0 becomes CHAINED */ + write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 1, 0x0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), + "32b->64b: CHAIN counter incremented and no overflow"); + + report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", + read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + + /* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */ + pmu_reset(); + write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + write_sysreg_s(0x3, PMCNTENSET_EL0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("counter #0=0x%lx, counter #1=0x%lx", + read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); + + write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(read_sysreg(pmovsclr_el0) == 1, + "overflow is expected on counter 0"); + report_info("counter #0=0x%lx, counter #1=0x%lx overflow=0x%lx", + read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), + read_sysreg(pmovsclr_el0)); +} + #endif /* @@ -792,6 +926,10 @@ int main(int argc, char *argv[]) report_prefix_push(argv[1]); test_chained_sw_incr(); report_prefix_pop(); + } else if (strcmp(argv[1], "pmu-chain-promotion") == 0) { + report_prefix_push(argv[1]); + test_chain_promotion(); + report_prefix_pop(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index d31dcbf6c56f..1b0c8c8c7eef 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -108,6 +108,12 @@ groups = pmu arch = arm64 extra_params = -append 'pmu-chained-sw-incr' +[pmu-chain-promotion] +file = pmu.flat +groups = pmu +arch = arm64 +extra_params = -append 'pmu-chain-promotion' + # Test PMU support (TCG) with -icount IPC=1 #[pmu-tcg-icount-1] #file = pmu.flat -- 2.25.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm