Re: [PATCH v2 06/14] arm64/hyp-stub: Enable access to ALLINT

Marc Zyngier
2022-12-05T17:50:38Z

On Sat, 12 Nov 2022 15:17:00 +0000,
Mark Brown <broonie@kernel.org> wrote:
>
> In order to use NMIs we need to ensure that traps are disabled for it so
> update HCRX_EL2 to ensure that TALLINT is not set when we detect support
> for NMIs.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/kernel/hyp-stub.S | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
> index 2ee18c860f2a..4e0b06467973 100644
> --- a/arch/arm64/kernel/hyp-stub.S
> +++ b/arch/arm64/kernel/hyp-stub.S
> @@ -151,6 +151,18 @@ SYM_CODE_START_LOCAL(__finalise_el2)
>
> .Lskip_sme:
>
> + // NMIs
> + __check_override id_aa64pfr1 ID_AA64PFR1_EL1_NMI_SHIFT 4 .Linit_nmi .Lskip_nmi

Err.., What makes sure that x1 contains id_aa64pfr1_el1, as per the
big fat warning at the beginning of the file?? If you have SME, x1
will contain some other junk... Really, this must be written as:

check_override id_aa64pfr1 ID_AA64PFR1_EL1_NMI_SHIFT .Linit_nmi .Lskip_nmi

> +.Linit_nmi:
> + mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
> + ubfx x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
> + cbz x1, .Lskip_nmi
> +
> + mrs_s x1, SYS_HCRX_EL2
> + and x1, x1, #~HCRX_EL2_TALLINT_MASK // Don't trap ALLINT

A nicer way of writing this is:

bic x1, x1, #HCRX_EL2_TALLINT_MASK

M.

--
Without deviation from the norm, progress is not possible.