From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Eric Auger <eric.auger@redhat.com>,
Mark Brown <broonie@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will@kernel.org>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Chase Conklin <chase.conklin@arm.com>,
Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
Darren Hart <darren@os.amperecomputing.com>,
Miguel Luis <miguel.luis@oracle.com>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v2 06/26] arm64: Add debug registers affected by HDFGxTR_EL2
Date: Fri, 28 Jul 2023 09:29:32 +0100 [thread overview]
Message-ID: <20230728082952.959212-7-maz@kernel.org> (raw)
In-Reply-To: <20230728082952.959212-1-maz@kernel.org>
The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
related registers. Add their encodings (and only that, because
we really don't care about what these registers actually do at
this stage).
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 76289339b43b..9dfd127be55a 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -194,6 +194,84 @@
#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
+#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
+#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
+#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
+#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
+#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
+#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
+#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
+
+#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
+#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
+#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
+
+#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
+#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
+#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
+#define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
+#define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
+#define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
+#define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
+#define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
+#define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
+#define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
+#define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
+#define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
+#define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
+#define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
+#define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
+#define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
+#define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
+#define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
+#define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
+#define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
+#define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
+#define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
+#define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
+#define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
+#define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
+#define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
+#define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
+#define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
+#define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
+#define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
+#define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
+#define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
+#define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
+#define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
+#define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
+#define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
+#define SYS_TRCIMSPEC0 sys_reg(2, 1, 0, 0, 7)
+#define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
+#define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
+#define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
+#define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
+#define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
+#define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
+#define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
+#define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
+#define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
+#define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
+#define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
+#define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
+#define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
+#define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
+#define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
+#define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
+#define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
+#define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
+#define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
+#define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
+#define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
+#define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
+#define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
+#define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
+#define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
+
+/* ETM */
+#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
+
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
--
2.34.1
next prev parent reply other threads:[~2023-07-28 8:30 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-28 8:29 [PATCH v2 00/26] KVM: arm64: NV trap forwarding infrastructure Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 01/26] arm64: Add missing VA CMO encodings Marc Zyngier
2023-07-28 10:47 ` Miguel Luis
2023-07-28 14:11 ` Catalin Marinas
2023-07-31 14:27 ` Zenghui Yu
2023-07-28 8:29 ` [PATCH v2 02/26] arm64: Add missing ERX*_EL1 encodings Marc Zyngier
2023-07-28 11:02 ` Miguel Luis
2023-07-28 14:12 ` Catalin Marinas
2023-07-31 14:27 ` Zenghui Yu
2023-07-28 8:29 ` [PATCH v2 03/26] arm64: Add missing DC ZVA/GVA/GZVA encodings Marc Zyngier
2023-07-28 11:20 ` Miguel Luis
2023-07-28 14:12 ` Catalin Marinas
2023-07-31 14:27 ` Zenghui Yu
2023-07-28 8:29 ` [PATCH v2 04/26] arm64: Add TLBI operation encodings Marc Zyngier
2023-07-28 14:13 ` Catalin Marinas
2023-07-28 14:25 ` Marc Zyngier
2023-07-28 15:49 ` Miguel Luis
2023-07-31 14:27 ` Zenghui Yu
2023-07-28 8:29 ` [PATCH v2 05/26] arm64: Add AT " Marc Zyngier
2023-07-28 14:13 ` Catalin Marinas
2023-07-31 9:55 ` Miguel Luis
2023-07-31 14:27 ` Zenghui Yu
2023-07-28 8:29 ` Marc Zyngier [this message]
2023-07-28 14:14 ` [PATCH v2 06/26] arm64: Add debug registers affected by HDFGxTR_EL2 Catalin Marinas
2023-07-31 16:41 ` Miguel Luis
2023-08-02 17:52 ` Marc Zyngier
2023-08-03 0:00 ` Miguel Luis
2023-08-07 12:40 ` Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 07/26] arm64: Add missing BRB/CFP/DVP/CPP instructions Marc Zyngier
2023-07-28 14:14 ` Catalin Marinas
2023-07-28 8:29 ` [PATCH v2 08/26] arm64: Add HDFGRTR_EL2 and HDFGWTR_EL2 layouts Marc Zyngier
2023-07-28 14:15 ` Catalin Marinas
2023-08-02 9:08 ` Miguel Luis
2023-07-28 8:29 ` [PATCH v2 09/26] arm64: Add feature detection for fine grained traps Marc Zyngier
2023-07-31 14:27 ` Zenghui Yu
2023-08-02 11:54 ` Miguel Luis
2023-07-28 8:29 ` [PATCH v2 10/26] KVM: arm64: Correctly handle ACCDATA_EL1 traps Marc Zyngier
2023-08-03 13:55 ` Miguel Luis
2023-07-28 8:29 ` [PATCH v2 11/26] KVM: arm64: Add missing HCR_EL2 trap bits Marc Zyngier
2023-08-04 13:57 ` Miguel Luis
2023-07-28 8:29 ` [PATCH v2 12/26] KVM: arm64: nv: Add FGT registers Marc Zyngier
2023-08-04 14:56 ` Miguel Luis
2023-07-28 8:29 ` [PATCH v2 13/26] KVM: arm64: Restructure FGT register switching Marc Zyngier
2023-07-28 17:23 ` Eric Auger
2023-07-28 17:26 ` Oliver Upton
2023-08-07 10:15 ` Miguel Luis
2023-07-28 8:29 ` [PATCH v2 14/26] KVM: arm64: nv: Add trap forwarding infrastructure Marc Zyngier
2023-07-28 18:33 ` Oliver Upton
2023-07-29 9:19 ` Marc Zyngier
2023-07-31 17:02 ` Oliver Upton
2023-07-28 8:29 ` [PATCH v2 15/26] KVM: arm64: nv: Add trap forwarding for HCR_EL2 Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 16/26] KVM: arm64: nv: Expose FEAT_EVT to nested guests Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 17/26] KVM: arm64: nv: Add trap forwarding for MDCR_EL2 Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 18/26] KVM: arm64: nv: Add trap forwarding for CNTHCTL_EL2 Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 19/26] KVM: arm64: nv: Add trap forwarding for HFGxTR_EL2 Marc Zyngier
2023-07-28 18:47 ` Oliver Upton
2023-07-29 9:20 ` Marc Zyngier
2023-08-07 13:14 ` Eric Auger
2023-07-28 8:29 ` [PATCH v2 20/26] KVM: arm64: nv: Add trap forwarding for HFGITR_EL2 Marc Zyngier
2023-08-07 13:30 ` Eric Auger
2023-07-28 8:29 ` [PATCH v2 21/26] KVM: arm64: nv: Add trap forwarding for HDFGxTR_EL2 Marc Zyngier
2023-08-07 17:19 ` Eric Auger
2023-08-07 19:00 ` Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 22/26] KVM: arm64: nv: Add SVC trap forwarding Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 23/26] KVM: arm64: nv: Add switching support for HFGxTR/HDFGxTR Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 24/26] KVM: arm64: nv: Expose FGT to nested guests Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 25/26] KVM: arm64: Move HCRX_EL2 switch to load/put on VHE systems Marc Zyngier
2023-07-28 8:29 ` [PATCH v2 26/26] KVM: arm64: nv: Add support for HCRX_EL2 Marc Zyngier
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