From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-178.mta0.migadu.com (out-178.mta0.migadu.com [91.218.175.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1A41154C16 for ; Wed, 19 Jun 2024 17:41:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.178 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718818869; cv=none; b=EPgODc6xzP+a+kH8lK+FKXdFkLMRG3lV3RRle5181R6/5Uhij463ftCJ8b2xQR2K+iyeUPVKKV0FBzOhnBjS01jvJqf9CV55EymVseSIK4jEmFuAoErEJIMnOTUmJvLqnJ/KNLLjKFm9m7inKU/mlCQwgpOcwVDGqX6cKhcGULs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718818869; c=relaxed/simple; bh=O9MO5ksgfZKE6Psjp/NK1WSZjNKbR3uQC4OGuUJZ1x8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Gt1CBq5d1Bv3lkiFqWRDECPsOdf6liWD94OD3nGZp29JcLpgY+vNa2ki2z94lVCI1aMy5zOeh3EhgaCkYEoAB8m4Qb9NzcDQdq0hJhDROFXZfCbBGMCnt+422ytFCV/ujBt4Dla5ojqmS9CqPPN9KR3BzhLTKx23f+/+zk6a9CA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=vwtNSwpV; arc=none smtp.client-ip=91.218.175.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="vwtNSwpV" X-Envelope-To: kvmarm@lists.linux.dev DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1718818866; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JFicmG6gjOgSjsYwgMKo9ydmBK5VIdzL4WrGLPRClyU=; b=vwtNSwpVzIQxtVqqJsRX9i/XyVLvP+HPJVfMS2FS76Gj/zFHOjiUbWlq9n4DbRQkVzBUqh Gvzfog5GjoJXaS4p5P1OCAsfAiidME6gcj7NrRJBBQF8HvCFVO0GGzlLTmZRnFeMg0KgNr bVi56t72BG+GfH9BOaOeNyZLhl7zP/w= X-Envelope-To: maz@kernel.org X-Envelope-To: james.morse@arm.com X-Envelope-To: suzuki.poulose@arm.com X-Envelope-To: yuzenghui@huawei.com X-Envelope-To: kvm@vger.kernel.org X-Envelope-To: sebott@redhat.com X-Envelope-To: shahuang@redhat.com X-Envelope-To: eric.auger@redhat.com X-Envelope-To: oliver.upton@linux.dev X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , James Morse , Suzuki K Poulose , Zenghui Yu , kvm@vger.kernel.org, Sebastian Ott , Shaoqin Huang , Eric Auger , Oliver Upton Subject: [PATCH v5 08/10] KVM: arm64: show writable masks for feature registers Date: Wed, 19 Jun 2024 17:40:34 +0000 Message-ID: <20240619174036.483943-9-oliver.upton@linux.dev> In-Reply-To: <20240619174036.483943-1-oliver.upton@linux.dev> References: <20240619174036.483943-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT From: Sebastian Ott Instead of using ~0UL provide the actual writable mask for non-id feature registers in the output of the KVM_ARM_GET_REG_WRITABLE_MASKS ioctl. This changes the mask for the CTR_EL0 and CLIDR_EL1 registers. Signed-off-by: Sebastian Ott Reviewed-by: Eric Auger Signed-off-by: Oliver Upton --- arch/arm64/kvm/sys_regs.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a12f3bdfb43d..d8d2a7880576 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2486,7 +2486,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, - .set_user = set_clidr }, + .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, @@ -4046,20 +4046,11 @@ int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range * if (!is_feature_id_reg(encoding) || !reg->set_user) continue; - /* - * For ID registers, we return the writable mask. Other feature - * registers return a full 64bit mask. That's not necessary - * compliant with a given revision of the architecture, but the - * RES0/RES1 definitions allow us to do that. - */ - if (is_vm_ftr_id_reg(encoding)) { - if (!reg->val || - (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) - continue; - val = reg->val; - } else { - val = ~0UL; + if (!reg->val || + (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { + continue; } + val = reg->val; if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) return -EFAULT; -- 2.45.2.627.g7a2c4fd464-goog