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Sat, 21 Dec 2024 08:45:51 -0500 (EST) Date: Sat, 21 Dec 2024 14:45:49 +0100 From: Janne Grunau To: Oliver Upton Cc: kvmarm@lists.linux.dev, Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev Subject: Re: [PATCH 00/18] KVM: arm64: Support FEAT_PMUv3 on Apple hardware Message-ID: <20241221134549.GA2917938@robin.jannau.net> References: <20241217212048.3709204-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20241217212048.3709204-1-oliver.upton@linux.dev> On Tue, Dec 17, 2024 at 01:20:30PM -0800, Oliver Upton wrote: > One of the interesting features of some Apple M* parts is an IMPDEF trap > that routes EL1/EL0 accesses of the PMUv3 registers to EL2. This allows > a hypervisor to emulate an architectural PMUv3 on top of the IMPDEF PMU > hardware present in the CPU. > > And if you squint, this _might_ look like a CPU erratum :-) > > This series takes advantage of these IMPDEF traps to provide PMUv3 to > KVM guests. As a starting point, only expose the fixed CPU cycle counter > and no event counters. Conveniently, this is enough to get Windows > running as a KVM guest on Apple hardware. > > I've tried to keep the deviation to a minimum by refactoring some of the > flows used for PMUv3, e.g. computing PMCEID from the arm_pmu bitmap > instead of reading hardware directly. > > RFC -> v1: > - Rebase to 6.13-rc3 > - Add support for 1 event counter in addition to CPU cycle counter > - Don't sneak past the PMU event filter (Marc) > - Have the PMU driver provide a PMUv3 -> HW event ID mapping (Marc) > > Tested on my M2 with Linux and Windows guests. If possible, I'd > appreciate someone testing on an M1 as I haven't added those MIDRs to > the erratum yet. Tested on M1 (t8103) with perf in a Linux guest and the patch below Tested-by: Janne Grunau I'll import this into the downstream asahi kernel as there was a request for performance counters to aid FEX-Emu development recently. Janne --- diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 441ee4ffc7709..45ef67ec970f5 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -195,6 +195,12 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, } static const struct midr_range impdef_pmuv3_cpus[] = { + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), + MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),