From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D6EC25E46A; Mon, 10 Feb 2025 18:42:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739212926; cv=none; b=FDY7+0q/b/PTWv0JHPyMlAWo4XjoDBKh6QsR4VpFp68/xLSBzDpj/QktPYNcyD+dzLrUSyEDGlZVpMPK+hZzglo3RAtc9cqkzO6FPxRGSiJa+PazdALmLa9yId6YOwC56k6KogjBAsEqx7vUT/CL3zZPAvC3gZ6ZTX0cNtwg1uw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739212926; c=relaxed/simple; bh=3biXRVPbF9WWOAm/jnoKLWbqKYvI6yleQgyfea1IVEc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ey8k6dwafa0s3vI7cNC6Z3S8shfblYyAxT4K3BXGMwrd28UpmcXcEHkVV+Y1xZGICZaz7r23+TRA4UyBU+H0jHEOwg6XUqvQPp4Oar4fnS8yAOkx9CtJamqky6Ou6qTpCEIZ+FBFfEzhZvxD2O6NYJnSi5wD2SYQHbhjVnldZ0I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GXs9ZdjA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GXs9ZdjA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D15A2C4CED1; Mon, 10 Feb 2025 18:42:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739212925; bh=3biXRVPbF9WWOAm/jnoKLWbqKYvI6yleQgyfea1IVEc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GXs9ZdjA65sJUFETmlzlBhs5+L9N6MPvGxbeqEem7MNtPQeHW/w4MR026Nmu2XJfO GSesN5TBE/7m2R+mDoXflE4E84lbGzQgo1MnWZ4LLAqp7pJC/4X0/KH7vHv1Ahz/pb VTwUnLbRes7aDiDQsigEUSCx0UOGTD1HBVM3RdanC4TOclnDCU90Mesle4qCRx1V9F KEwWjeF6vjZmdHcPp8s2v7J0PgOD3YPLWHUHSNtNeK0fNs/9BtkkxSYDTIaaEt5gRU bXFrMs1o/+Pe0lnW9wCYRSDXqbz1tsK7fCLhMOXQ7brYm8CyDstpUZCgJvmz3vOdPg 4xD8KXSGx/Bjw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1thYjJ-002g2I-Cx; Mon, 10 Feb 2025 18:42:01 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Mark Rutland , Fuad Tabba Subject: [PATCH 17/18] KVM: arm64: Validate FGT register descriptions against RES0 masks Date: Mon, 10 Feb 2025 18:41:48 +0000 Message-Id: <20250210184150.2145093-18-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250210184150.2145093-1-maz@kernel.org> References: <20250210184150.2145093-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, mark.rutland@arm.com, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false In order to point out to the unsuspecting KVM hacker that they are missing something somewhere, validate that the known FGT bits do not intersect with the corresponding RES0 mask, as computed at boot time. THis check is also performed at boot time, ensuring that there is no runtime overhead. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/config.c | 29 +++++++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 2 ++ 3 files changed, 32 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index f9975b5f8907a..b537adc5c5557 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1577,5 +1577,6 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); +void check_feature_map(void); #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index 0a68555068f11..c9dff71006bf4 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -482,6 +482,35 @@ static struct reg_bits_to_feat_map hafgrtr_feat_map[] = { FEAT_AMUv1), }; +static void __init check_feat_map(struct reg_bits_to_feat_map *map, + int map_size, u64 res0, const char *str) +{ + u64 mask = 0; + + for (int i = 0; i < map_size; i++) + mask |= map[i].bits; + + if (mask != ~res0) + kvm_err("Undefined %s behaviour, bits %016llx\n", + str, mask ^ ~res0); +} + +void __init check_feature_map(void) +{ + check_feat_map(hfgrtr_feat_map, ARRAY_SIZE(hfgrtr_feat_map), + hfgrtr_masks.res0, hfgrtr_masks.str); + check_feat_map(hfgwtr_feat_map, ARRAY_SIZE(hfgwtr_feat_map), + hfgwtr_masks.res0, hfgwtr_masks.str); + check_feat_map(hfgitr_feat_map, ARRAY_SIZE(hfgitr_feat_map), + hfgitr_masks.res0, hfgitr_masks.str); + check_feat_map(hdfgrtr_feat_map, ARRAY_SIZE(hdfgrtr_feat_map), + hdfgrtr_masks.res0, hdfgrtr_masks.str); + check_feat_map(hdfgwtr_feat_map, ARRAY_SIZE(hdfgwtr_feat_map), + hdfgwtr_masks.res0, hdfgwtr_masks.str); + check_feat_map(hafgrtr_feat_map, ARRAY_SIZE(hafgrtr_feat_map), + hafgrtr_masks.res0, hafgrtr_masks.str); +} + static bool idreg_feat_match(struct kvm *kvm, struct reg_bits_to_feat_map *map) { u64 regval = kvm->arch.id_regs[map->regidx]; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d3990ceaa59c2..89fc07c57e438 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -5058,6 +5058,8 @@ int __init kvm_sys_reg_table_init(void) ret = populate_nv_trap_config(); + check_feature_map(); + for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) ret = populate_sysreg_config(sys_reg_descs + i, i); -- 2.39.2