From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87BF425A2D5; Mon, 10 Feb 2025 18:42:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739212920; cv=none; b=fJtqLNbiZMzirFhqtfNvXuDuCnIJ1wESwt3/T3G1sdslqX0gQlNYgVPC2hg/I6/XHoI04FPe30lupRt3EgHZ3oXMyvy8CgGOyl+qGs5/S6lGJZ3ntu12VXKHUGRS0kIjXezj1EOBG6KLha9YlT5F4dC37G4PfWlcOUVlr+naEqI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739212920; c=relaxed/simple; bh=9WGEF6A0ADnv6z6hchcc2hNLlsWnoeEm6HgulDZDTAw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tLKtokN37QcMb8/OskigMUOa/pUMfcxPmYGjUXoVho9WJayEud2QUdteDXurpLA25W6WiKjn9oTU9gvPBYGyl2F4wB/3/EOTTZCylrxA8uY4g8LF8Du0eZB/a8h79XLTU3xXIiL8WikMk+MkwkYwkQ8AUhq6bM6LwLpAMNNHniU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TNIuKE4x; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TNIuKE4x" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BDE8C4CEE7; Mon, 10 Feb 2025 18:42:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739212920; bh=9WGEF6A0ADnv6z6hchcc2hNLlsWnoeEm6HgulDZDTAw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TNIuKE4xSKZxikrwD88Pi2o/BV7XaNFYWnnTjcRQh+lRp/OwalMEGGIfJyDBM4wUC oiudFlhlaCAjeqf16bkFPzHfHh9MLg7k/x5f16YD2IV6Mo9VlbBZkPN+uhRuDgiPmS nfrLvEfym67pneVwXA3G3RlIjdx55JL42iOwH36Qp7YxmGAzEcmGBFSuQjuPk4SnEK /f6c5MHQGNuFs16qkhg3DhSjHEpP7HYm6Z7aWziAFqeCh/hj4L5d9884z/LHPmCEDD qgSP8LDGC/C75o/YNUSVBguFEJZ08gmw+SCavrX71r2GHb/oTsjpoRX50tjGNtV1U6 iQl4vZCwaSGkw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1thYjG-002g2I-BF; Mon, 10 Feb 2025 18:41:58 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Mark Rutland , Fuad Tabba Subject: [PATCH 05/18] KVM: arm64: Don't treat HCRX_EL2 as a FGT register Date: Mon, 10 Feb 2025 18:41:36 +0000 Message-Id: <20250210184150.2145093-6-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250210184150.2145093-1-maz@kernel.org> References: <20250210184150.2145093-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, mark.rutland@arm.com, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Treating HCRX_EL2 as yet another FGT register seems excessive, and gets in a way of further improvements. It is actually simpler to just be explicit about the masking, so just to that. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/include/hyp/switch.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index f838a45665f26..25a7ff5012ed6 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -261,12 +261,9 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) if (cpus_have_final_cap(ARM64_HAS_HCX)) { u64 hcrx = vcpu->arch.hcrx_el2; if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) { - u64 clr = 0, set = 0; - - compute_clr_set(vcpu, HCRX_EL2, clr, set); - - hcrx |= set; - hcrx &= ~clr; + u64 val = __vcpu_sys_reg(vcpu, HCRX_EL2); + hcrx |= val & __HCRX_EL2_MASK; + hcrx &= ~(~val & __HCRX_EL2_nMASK); } write_sysreg_s(hcrx, SYS_HCRX_EL2); -- 2.39.2