From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C70802528E8; Sat, 26 Apr 2025 12:28:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745670535; cv=none; b=LtWDxwoUEjXumrjbQY+seBCT315O8+YD9iQRWyMGFNjmOEEz7vO0ZMGOhKKtDXHGP+qPROyziQ5RWF5tQDkoDDNPnMrdrb1K/64rh85JTOEDy8dvOKT4U0+FgKxVeKMt0auaJ38yDZbC2cPy8wMs8gYMqEbATaPgO3vOetjjqAs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745670535; c=relaxed/simple; bh=4gVu6PuCEYwqR8T4hiE7L+z2SsXJBvzsxceLEkn+bGU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Pr0TslT/WQtqevCSitLu84KIQFwsSbv9UM2+ob04BRh63wLBZQcPSxaZ50Za7ADwaEQECwo0eesmfViVAuH8XroVr8rYbogP4YUgL2UmhepcSQRYx0D9N7s1WNB8+zks9P/5XgDUgrHKzuD0jEFEIgTZK6s6ACHSMqSj0fBhJ0M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WFaZcCno; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WFaZcCno" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A743DC4CEEC; Sat, 26 Apr 2025 12:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745670535; bh=4gVu6PuCEYwqR8T4hiE7L+z2SsXJBvzsxceLEkn+bGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WFaZcCnoqGpgjdGNVJTa59v3BikfKaZBdg/P0YYeBtTp06cJNWU27Du6nuvUrDMlt QIYMwMJF1Z/Hk33FU/39kUKs8FgCo7Fu+ThNxiCaczXQ8vgo7HBJFRvAGSCCQzZdrH oIVxeOIu/0C96egvwnZT8iMLC3n3lY4FAQ4gogUrwSGLg/1ur4mvuy0fXIcrEm2wyS SaxVSgABZMWL3gq+n1/7IxM1TwGdWRRzwmESLCbwo8ZuIhS3psXFtd8PDjOfoXdpDe ZvN+izP+naGm4RuWSS+Owow2JINM1Pchvx9T5k8TWr7Ndm6v2b1gLU+XcbxTttWY26 A6mI6El7Vd6RQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1u8eeL-0092VH-Qh; Sat, 26 Apr 2025 13:28:53 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Mark Rutland , Fuad Tabba , Will Deacon , Catalin Marinas Subject: [PATCH v3 19/42] KVM: arm64: Don't treat HCRX_EL2 as a FGT register Date: Sat, 26 Apr 2025 13:28:13 +0100 Message-Id: <20250426122836.3341523-20-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250426122836.3341523-1-maz@kernel.org> References: <20250426122836.3341523-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, mark.rutland@arm.com, tabba@google.com, will@kernel.org, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Treating HCRX_EL2 as yet another FGT register seems excessive, and gets in a way of further improvements. It is actually simpler to just be explicit about the masking, so just to that. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/include/hyp/switch.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 3150e42d79341..027d05f308f75 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -261,12 +261,9 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) if (cpus_have_final_cap(ARM64_HAS_HCX)) { u64 hcrx = vcpu->arch.hcrx_el2; if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) { - u64 clr = 0, set = 0; - - compute_clr_set(vcpu, HCRX_EL2, clr, set); - - hcrx |= set; - hcrx &= ~clr; + u64 val = __vcpu_sys_reg(vcpu, HCRX_EL2); + hcrx |= val & __HCRX_EL2_MASK; + hcrx &= ~(~val & __HCRX_EL2_nMASK); } write_sysreg_s(hcrx, SYS_HCRX_EL2); -- 2.39.2