From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Fuad Tabba <tabba@google.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH v3 21/42] KVM: arm64: Compute FGT masks from KVM's own FGT tables
Date: Sat, 26 Apr 2025 13:28:15 +0100 [thread overview]
Message-ID: <20250426122836.3341523-22-maz@kernel.org> (raw)
In-Reply-To: <20250426122836.3341523-1-maz@kernel.org>
In the process of decoupling KVM's view of the FGT bits from the
wider architectural state, use KVM's own FGT tables to build
a synthetic view of what is actually known.
This allows for some checking along the way.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/include/asm/kvm_host.h | 14 ++++
arch/arm64/kvm/emulate-nested.c | 106 ++++++++++++++++++++++++++++++
2 files changed, 120 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 7a1ef5be7efb2..95fedd27f4bb8 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -607,6 +607,20 @@ struct kvm_sysreg_masks {
} mask[NR_SYS_REGS - __SANITISED_REG_START__];
};
+struct fgt_masks {
+ const char *str;
+ u64 mask;
+ u64 nmask;
+ u64 res0;
+};
+
+extern struct fgt_masks hfgrtr_masks;
+extern struct fgt_masks hfgwtr_masks;
+extern struct fgt_masks hfgitr_masks;
+extern struct fgt_masks hdfgrtr_masks;
+extern struct fgt_masks hdfgwtr_masks;
+extern struct fgt_masks hafgrtr_masks;
+
struct kvm_cpu_context {
struct user_pt_regs regs; /* sp = sp_el0 */
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 52a2d63a667c9..528b33fcfcfd6 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -2033,6 +2033,105 @@ static u32 encoding_next(u32 encoding)
return sys_reg(op0 + 1, 0, 0, 0, 0);
}
+#define FGT_MASKS(__n, __m) \
+ struct fgt_masks __n = { .str = #__m, .res0 = __m, }
+
+FGT_MASKS(hfgrtr_masks, HFGRTR_EL2_RES0);
+FGT_MASKS(hfgwtr_masks, HFGWTR_EL2_RES0);
+FGT_MASKS(hfgitr_masks, HFGITR_EL2_RES0);
+FGT_MASKS(hdfgrtr_masks, HDFGRTR_EL2_RES0);
+FGT_MASKS(hdfgwtr_masks, HDFGWTR_EL2_RES0);
+FGT_MASKS(hafgrtr_masks, HAFGRTR_EL2_RES0);
+
+static __init bool aggregate_fgt(union trap_config tc)
+{
+ struct fgt_masks *rmasks, *wmasks;
+
+ switch (tc.fgt) {
+ case HFGRTR_GROUP:
+ rmasks = &hfgrtr_masks;
+ wmasks = &hfgwtr_masks;
+ break;
+ case HDFGRTR_GROUP:
+ rmasks = &hdfgrtr_masks;
+ wmasks = &hdfgwtr_masks;
+ break;
+ case HAFGRTR_GROUP:
+ rmasks = &hafgrtr_masks;
+ wmasks = NULL;
+ break;
+ case HFGITR_GROUP:
+ rmasks = &hfgitr_masks;
+ wmasks = NULL;
+ break;
+ }
+
+ /*
+ * A bit can be reserved in either the R or W register, but
+ * not both.
+ */
+ if ((BIT(tc.bit) & rmasks->res0) &&
+ (!wmasks || (BIT(tc.bit) & wmasks->res0)))
+ return false;
+
+ if (tc.pol)
+ rmasks->mask |= BIT(tc.bit) & ~rmasks->res0;
+ else
+ rmasks->nmask |= BIT(tc.bit) & ~rmasks->res0;
+
+ if (wmasks) {
+ if (tc.pol)
+ wmasks->mask |= BIT(tc.bit) & ~wmasks->res0;
+ else
+ wmasks->nmask |= BIT(tc.bit) & ~wmasks->res0;
+ }
+
+ return true;
+}
+
+static __init int check_fgt_masks(struct fgt_masks *masks)
+{
+ unsigned long duplicate = masks->mask & masks->nmask;
+ u64 res0 = masks->res0;
+ int ret = 0;
+
+ if (duplicate) {
+ int i;
+
+ for_each_set_bit(i, &duplicate, 64) {
+ kvm_err("%s[%d] bit has both polarities\n",
+ masks->str, i);
+ }
+
+ ret = -EINVAL;
+ }
+
+ masks->res0 = ~(masks->mask | masks->nmask);
+ if (masks->res0 != res0)
+ kvm_info("Implicit %s = %016llx, expecting %016llx\n",
+ masks->str, masks->res0, res0);
+
+ return ret;
+}
+
+static __init int check_all_fgt_masks(int ret)
+{
+ static struct fgt_masks * const masks[] __initconst = {
+ &hfgrtr_masks,
+ &hfgwtr_masks,
+ &hfgitr_masks,
+ &hdfgrtr_masks,
+ &hdfgwtr_masks,
+ &hafgrtr_masks,
+ };
+ int err = 0;
+
+ for (int i = 0; i < ARRAY_SIZE(masks); i++)
+ err |= check_fgt_masks(masks[i]);
+
+ return ret ?: err;
+}
+
int __init populate_nv_trap_config(void)
{
int ret = 0;
@@ -2097,8 +2196,15 @@ int __init populate_nv_trap_config(void)
ret = xa_err(prev);
print_nv_trap_error(fgt, "Failed FGT insertion", ret);
}
+
+ if (!aggregate_fgt(tc)) {
+ ret = -EINVAL;
+ print_nv_trap_error(fgt, "FGT bit is reserved", ret);
+ }
}
+ ret = check_all_fgt_masks(ret);
+
kvm_info("nv: %ld fine grained trap handlers\n",
ARRAY_SIZE(encoding_to_fgt));
--
2.39.2
next prev parent reply other threads:[~2025-04-26 12:28 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-26 12:27 [PATCH v3 00/42] KVM: arm64: Revamp Fine Grained Trap handling Marc Zyngier
2025-04-26 12:27 ` [PATCH v3 01/42] arm64: sysreg: Add ID_AA64ISAR1_EL1.LS64 encoding for FEAT_LS64WB Marc Zyngier
2025-04-29 13:34 ` Joey Gouly
2025-04-26 12:27 ` [PATCH v3 02/42] arm64: sysreg: Update ID_AA64MMFR4_EL1 description Marc Zyngier
2025-04-29 13:38 ` Joey Gouly
2025-04-26 12:27 ` [PATCH v3 03/42] arm64: sysreg: Add layout for HCR_EL2 Marc Zyngier
2025-04-29 14:02 ` Joey Gouly
2025-04-26 12:27 ` [PATCH v3 04/42] arm64: sysreg: Replace HGFxTR_EL2 with HFG{R,W}TR_EL2 Marc Zyngier
2025-04-29 13:07 ` Ben Horgan
2025-04-29 14:26 ` Joey Gouly
2025-05-01 13:20 ` Marc Zyngier
2025-04-26 12:27 ` [PATCH v3 05/42] arm64: sysreg: Update ID_AA64PFR0_EL1 description Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 06/42] arm64: sysreg: Update PMSIDR_EL1 description Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 07/42] arm64: sysreg: Update TRBIDR_EL1 description Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 08/42] arm64: sysreg: Add registers trapped by HFG{R,W}TR2_EL2 Marc Zyngier
2025-05-01 10:11 ` Joey Gouly
2025-05-01 13:46 ` Marc Zyngier
2025-05-01 13:52 ` Joey Gouly
2025-04-26 12:28 ` [PATCH v3 09/42] arm64: sysreg: Add registers trapped by HDFG{R,W}TR2_EL2 Marc Zyngier
2025-04-29 13:07 ` Ben Horgan
2025-04-29 14:10 ` Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 10/42] arm64: sysreg: Add system instructions trapped by HFGIRT2_EL2 Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 11/42] arm64: Remove duplicated sysreg encodings Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 12/42] arm64: tools: Resync sysreg.h Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 13/42] arm64: Add syndrome information for trapped LD64B/ST64B{,V,V0} Marc Zyngier
2025-05-01 10:17 ` Joey Gouly
2025-04-26 12:28 ` [PATCH v3 14/42] arm64: Add FEAT_FGT2 capability Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 15/42] KVM: arm64: Tighten handling of unknown FGT groups Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 16/42] KVM: arm64: Simplify handling of negative FGT bits Marc Zyngier
2025-05-01 10:43 ` Joey Gouly
2025-04-26 12:28 ` [PATCH v3 17/42] KVM: arm64: Handle trapping of FEAT_LS64* instructions Marc Zyngier
2025-04-29 13:08 ` Ben Horgan
2025-05-01 11:01 ` Joey Gouly
2025-04-26 12:28 ` [PATCH v3 18/42] KVM: arm64: Restrict ACCDATA_EL1 undef to FEAT_ST64_ACCDATA being disabled Marc Zyngier
2025-04-29 13:08 ` Ben Horgan
2025-04-26 12:28 ` [PATCH v3 19/42] KVM: arm64: Don't treat HCRX_EL2 as a FGT register Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 20/42] KVM: arm64: Plug FEAT_GCS handling Marc Zyngier
2025-04-26 12:28 ` Marc Zyngier [this message]
2025-05-01 11:32 ` [PATCH v3 21/42] KVM: arm64: Compute FGT masks from KVM's own FGT tables Joey Gouly
2025-04-26 12:28 ` [PATCH v3 22/42] KVM: arm64: Add description of FGT bits leading to EC!=0x18 Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 23/42] KVM: arm64: Use computed masks as sanitisers for FGT registers Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 24/42] KVM: arm64: Unconditionally configure fine-grain traps Marc Zyngier
2025-04-29 13:08 ` Ben Horgan
2025-04-29 13:49 ` Marc Zyngier
2025-04-29 14:09 ` Ben Horgan
2025-04-26 12:28 ` [PATCH v3 25/42] KVM: arm64: Propagate FGT masks to the nVHE hypervisor Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 26/42] KVM: arm64: Use computed FGT masks to setup FGT registers Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 27/42] KVM: arm64: Remove hand-crafted masks for " Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 28/42] KVM: arm64: Use KVM-specific HCRX_EL2 RES0 mask Marc Zyngier
2025-05-01 13:33 ` Joey Gouly
2025-04-26 12:28 ` [PATCH v3 29/42] KVM: arm64: Handle PSB CSYNC traps Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 30/42] KVM: arm64: Switch to table-driven FGU configuration Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 31/42] KVM: arm64: Validate FGT register descriptions against RES0 masks Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 32/42] KVM: arm64: Use FGT feature maps to drive RES0 bits Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 33/42] KVM: arm64: Allow kvm_has_feat() to take variable arguments Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 34/42] KVM: arm64: Use HCRX_EL2 feature map to drive fixed-value bits Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 35/42] KVM: arm64: Use HCR_EL2 " Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 36/42] KVM: arm64: Add FEAT_FGT2 registers to the VNCR page Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 37/42] KVM: arm64: Add sanitisation for FEAT_FGT2 registers Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 38/42] KVM: arm64: Add trap routing " Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 39/42] KVM: arm64: Add context-switch " Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 40/42] KVM: arm64: Allow sysreg ranges for FGT descriptors Marc Zyngier
2025-04-29 13:08 ` Ben Horgan
2025-04-26 12:28 ` [PATCH v3 41/42] KVM: arm64: Add FGT descriptors for FEAT_FGT2 Marc Zyngier
2025-04-29 13:09 ` Ben Horgan
2025-04-29 14:30 ` Marc Zyngier
2025-04-26 12:28 ` [PATCH v3 42/42] KVM: arm64: Handle TSB CSYNC traps Marc Zyngier
2025-04-28 18:33 ` [PATCH v3 00/42] KVM: arm64: Revamp Fine Grained Trap handling Ganapatrao Kulkarni
2025-04-28 21:42 ` Marc Zyngier
2025-04-29 7:34 ` Marc Zyngier
2025-04-29 14:30 ` Ganapatrao Kulkarni
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