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Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 125 ++++++++++++++++++ .../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 10 ++ 2 files changed, 135 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index e45b4e50b1e4..32f199aeec9e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -8,6 +8,7 @@ #include #include +#include #include "arm_smmu_v3.h" #include "../arm-smmu-v3.h" @@ -140,6 +141,8 @@ static int smmu_init(void) goto out_reclaim_smmu; } + BUILD_BUG_ON(sizeof(hyp_spinlock_t) != sizeof(u32)); + return 0; out_reclaim_smmu: @@ -150,6 +153,127 @@ static int smmu_init(void) return ret; } +static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, + struct user_pt_regs *regs, + u64 esr, u32 off) +{ + bool is_write = esr & ESR_ELx_WNR; + unsigned int len = BIT((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); + int rd = (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; + const u64 read_write = -1ULL; + const u64 no_access = 0; + u64 mask = no_access; + const u64 read_only = is_write ? no_access : read_write; + u64 val = regs->regs[rd]; + + switch (off) { + case ARM_SMMU_IDR0: + /* Clear stage-2 support, hide MSI to avoid write back to cmdq */ + mask = read_only & ~(IDR0_S2P | IDR0_VMID16 | IDR0_MSI | IDR0_HYP); + WARN_ON(len != sizeof(u32)); + break; + /* Passthrough the register access for bisectiblity, handled later */ + case ARM_SMMU_CMDQ_BASE: + case ARM_SMMU_CMDQ_PROD: + case ARM_SMMU_CMDQ_CONS: + case ARM_SMMU_STRTAB_BASE: + case ARM_SMMU_STRTAB_BASE_CFG: + case ARM_SMMU_GBPA: + mask = read_write; + break; + case ARM_SMMU_CR0: + mask = read_write; + WARN_ON(len != sizeof(u32)); + break; + case ARM_SMMU_CR1: { + /* Based on Linux implementation */ + u64 cr2_template = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB); + /* Don't mess with shareability/cacheability. */ + if (is_write) + WARN_ON(val != cr2_template); + mask = read_write; + WARN_ON(len != sizeof(u32)); + break; + } + /* + * These should be safe, just enforce RO or RW and size according to architecture. + * There are some other registers that are not used by Linux as IDR2, IDR4 + * that won't be allowed. + */ + case ARM_SMMU_EVTQ_PROD + SZ_64K: + case ARM_SMMU_EVTQ_CONS + SZ_64K: + case ARM_SMMU_EVTQ_IRQ_CFG1: + case ARM_SMMU_EVTQ_IRQ_CFG2: + case ARM_SMMU_PRIQ_PROD + SZ_64K: + case ARM_SMMU_PRIQ_CONS + SZ_64K: + case ARM_SMMU_PRIQ_IRQ_CFG1: + case ARM_SMMU_PRIQ_IRQ_CFG2: + case ARM_SMMU_GERRORN: + case ARM_SMMU_GERROR_IRQ_CFG1: + case ARM_SMMU_GERROR_IRQ_CFG2: + case ARM_SMMU_IRQ_CTRLACK: + case ARM_SMMU_IRQ_CTRL: + case ARM_SMMU_CR0ACK: + case ARM_SMMU_CR2: + /* These are 32 bit registers. */ + WARN_ON(len != sizeof(u32)); + fallthrough; + case ARM_SMMU_EVTQ_BASE: + case ARM_SMMU_EVTQ_IRQ_CFG0: + case ARM_SMMU_PRIQ_BASE: + case ARM_SMMU_PRIQ_IRQ_CFG0: + case ARM_SMMU_GERROR_IRQ_CFG0: + mask = read_write; + break; + case ARM_SMMU_IIDR: + case ARM_SMMU_IDR5: + case ARM_SMMU_IDR3: + case ARM_SMMU_IDR1: + case ARM_SMMU_GERROR: + WARN_ON(len != sizeof(u32)); + mask = read_only; + }; + + if (WARN_ON(!mask)) + goto out_ret; + + if (is_write) { + if (len == sizeof(u64)) + writeq_relaxed(regs->regs[rd] & mask, smmu->base + off); + else + writel_relaxed(regs->regs[rd] & mask, smmu->base + off); + } else { + if (len == sizeof(u64)) + regs->regs[rd] = readq_relaxed(smmu->base + off) & mask; + else + regs->regs[rd] = readl_relaxed(smmu->base + off) & mask; + } + +out_ret: + return true; +} + +static bool smmu_dabt_handler(struct user_pt_regs *regs, u64 esr, u64 addr) +{ + struct hyp_arm_smmu_v3_device *smmu; + bool ret; + + for_each_smmu(smmu) { + if (addr < smmu->mmio_addr || addr >= smmu->mmio_addr + smmu->mmio_size) + continue; + hyp_spin_lock(&smmu->lock); + ret = smmu_dabt_device(smmu, regs, esr, addr - smmu->mmio_addr); + hyp_spin_unlock(&smmu->lock); + return ret; + } + return false; +} + static void smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot) { } @@ -158,4 +282,5 @@ static void smmu_host_stage2_idmap(phys_addr_t start, phys_addr_t end, int prot) struct kvm_iommu_ops smmu_ops = { .init = smmu_init, .host_stage2_idmap = smmu_host_stage2_idmap, + .dabt_handler = smmu_dabt_handler, }; diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h index 3550fa695539..dfeaed728982 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h @@ -4,6 +4,10 @@ #include +#ifdef __KVM_NVHE_HYPERVISOR__ +#include +#endif + /* * Parameters from the trusted host: * @mmio_addr base address of the SMMU registers @@ -16,6 +20,7 @@ * @oas PA size * @pgsize_bitmap Supported page sizes * @sid_bits Max number of SID bits supported + * @lock Lock to protect SMMU */ struct hyp_arm_smmu_v3_device { phys_addr_t mmio_addr; @@ -26,6 +31,11 @@ struct hyp_arm_smmu_v3_device { unsigned long oas; unsigned long pgsize_bitmap; unsigned int sid_bits; +#ifdef __KVM_NVHE_HYPERVISOR__ + hyp_spinlock_t lock; +#else + u32 lock; +#endif }; extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count); -- 2.51.0.rc1.167.g924127e9c0-goog