From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E4AC37BE8F for ; Wed, 15 Apr 2026 11:56:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776254183; cv=none; b=uK+f08QrIzzHXW+MvX2qRfP5L3w6xNzYZQBufuuAEtzrH9zUC7fBOXyjhgUUMEVw10z8QDA5q/IlbBkakkWEAWHeauxoEznSkXoZAaOv7cfPReFwRK7a0v7IVDIG5MpOUrl+n3fm8mOZl4uibXVtFvuycq7wKK0a28PSjNyH9aI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776254183; c=relaxed/simple; bh=BZz1qnB2VX9ACDvWCNyOh7Vg0dUXghFKOcw3QAKYdvE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uRqGrfnYJHmTfUzSwiJHSUbMGn3VT2bIh/HxH7+JJOBZixwycNIkxWWS06ye+uACRsOiEqS1Lo59bX/8z7SgmJFGYTlBQXzO26amiQ4fyNWmoCQy+VduTLjh85pXWJ/mdiAaRt47KJrmjBX6Q3pYelzeo8vIG4JyUKVjrefFnuY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lTYffitC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lTYffitC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 463D0C2BCB7; Wed, 15 Apr 2026 11:56:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776254183; bh=BZz1qnB2VX9ACDvWCNyOh7Vg0dUXghFKOcw3QAKYdvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lTYffitC3UFpsiCdds5vDJSft+agSYI1ZCIhgKYNf4shjKCojmzcQRnSBa/4rLjBh tJuup+uqU5TvPjdAbQ/NU45yI+UJPT6mFTLHeg2JcU13DjZl/GovFVJwnW3P0bbclt NMw9pmL0sILMZLOUBdkf9/jeB+j6P6Qdz2oexaqlkj/ggVmfG5VPOfOSKgx9FDW4QI g5aV8uqqkdH4x0/8a99HSlndrlGb3tlt8QqRceldnrmImFlBt+f/Wse3m/kktT2PWy 0iWwgDNz8oH4pTKgTMQ7sECM9M8m42uHTJ5ygnjZxceRRRN/m9RD7Afvu0wvhrldZC RcX8VCdm2ALIA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wCyqz-0000000Bqsi-1NGV; Wed, 15 Apr 2026 11:56:21 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Sascha Bischoff Subject: [PATCH 11/18] KVM: arm64: vgic-v5: Atomically assign bits to PPI DVI bitmap Date: Wed, 15 Apr 2026 12:55:52 +0100 Message-ID: <20260415115559.2227718-12-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260415115559.2227718-1-maz@kernel.org> References: <20260415115559.2227718-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, sascha.bischoff@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false From: Sascha Bischoff For GICv5 guests we make use of the DVI mechanism for PPIs where possible. When mapping a virtual irq to a physical one for a GICv5 guest, the corresponding bit in the DVI bitmap is set. When unmapping, said bit is cleared again. The key user of this mechanism is the arch timer. The existing code used the non-atomic __assign_bit() rather than doing the update atomically. This could technically result in losing state if a second PPI's DVI bit were being manipulated concurrently. Each individual bit within the DVI bitmap is guarded using vgic_irq->irq_lock, but there's no locking for the overall bitmap. Therefore, switch to using the atomic assign_bit() function instead. Fixes: 5a98d0e17e59 ("KVM: arm64: gic-v5: Implement direct injection of PPIs") Link: https://sashiko.dev/#/patchset/20260319154937.3619520-1-sascha.bischoff%40arm.com Signed-off-by: Sascha Bischoff Signed-off-by: Marc Zyngier --- arch/arm64/kvm/vgic/vgic-v5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c index 7916bd8d564ef..d4789ff3e7402 100644 --- a/arch/arm64/kvm/vgic/vgic-v5.c +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -272,7 +272,7 @@ void vgic_v5_set_ppi_dvi(struct kvm_vcpu *vcpu, struct vgic_irq *irq, bool dvi) lockdep_assert_held(&irq->irq_lock); ppi = vgic_v5_get_hwirq_id(irq->intid); - __assign_bit(ppi, cpu_if->vgic_ppi_dvir, dvi); + assign_bit(ppi, cpu_if->vgic_ppi_dvir, dvi); } static const struct irq_ops vgic_v5_ppi_irq_ops = { -- 2.47.3