Re: [PATCH 6.6 v3 4/6] KVM: arm64: Initialize HCR_EL2.E2H early

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Preexisting sysreg write paths in `___kvm_hyp_init` and `init_el2_state` macros omit the architecturally required `isb` immediately after writing control-plane system registers.
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--- Patch [4]: [PATCH 6.6 v3 4/6] KVM: arm64: Initialize HCR_EL2.E2H early ---
(Note: The format of this report is altered to provide a free-form summary instead of quoting the patch code directly, due to recitation restrictions.)

commit 726047e1aa205da54b261630927b54303540481f
Author: Mark Rutland <mark.rutland@arm.com>

KVM: arm64: Initialize HCR_EL2.E2H early

This commit initializes HCR_EL2.E2H early in KVM PSCI entry points to avoid
consuming an uninitialized value on CPUs without FEAT_E2H0. It factors out
existing head.S logic into a new init_el2_hcr macro.

Link: https://lore.kernel.org/r/20250227180526.1204723-2-mark.rutland@arm.com

[Severity: High]
This isn't a bug introduced by this patch, but there appears to be a
pre-existing issue with missing context synchronization events in the EL2
initialization paths.

In arch/arm64/kvm/hyp/nvhe/hyp-init.S:___kvm_hyp_init, writes to mair_el2,
hcr_el2, and vttbr_el2 are followed by memory loads or other operations
without an immediate isb instruction.

Similarly, in arch/arm64/include/asm/el2_setup.h:__init_el2_hcrx, the write
to SYS_HCRX_EL2 is followed by a branch rather than an isb. Also, in
__init_el2_timers within the same file, cnthctl_el2 and cntvoff_el2 are
written consecutively without an isb between or immediately after them.

Could this cause the CPU to execute subsequent instructions under a stale
architectural configuration, potentially leading to unpredictable behavior
or unexpected traps during hypervisor setup?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260709223604.12934-1-coltonlewis@google.com?part=4