Re: [PATCH v5 47/49] KVM: selftests: Add VGICv5 LPI delivery tests

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The system instruction GIC CDEOI requires the fixed register XZR, but is emitted using a compiler constraint which may select a general-purpose register.
--

--- Patch [47]: [PATCH v5 47/49] KVM: selftests: Add VGICv5 LPI delivery tests ---
commit 1dca3130863c08b0c3a19e09294df6edd1534a20
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: selftests: Add VGICv5 LPI delivery tests

Add a two-VPE VGICv5 LPI delivery test. Exercise the virtual IRS ID
registers and IST base configuration path before checking interrupt
delivery.

> diff --git a/tools/testing/selftests/kvm/arm64/vgic_v5.c b/tools/testing/selftests/kvm/arm64/vgic_v5.c
> index 23fbd2db50c43..71bda5661c74e 100644
> --- a/tools/testing/selftests/kvm/arm64/vgic_v5.c
> +++ b/tools/testing/selftests/kvm/arm64/vgic_v5.c

[ ... ]

> @@ -209,6 +298,67 @@ static void guest_spi_line_code(void)
>  		wfi();
>  }
>  
> +static void guest_lpi_irq_handler(struct ex_regs *regs)
> +{
> +	u32 vcpu_id = guest_get_vcpuid();
> +	u32 expected_lpi = vcpu_id ? LPI_TEST_TO_VPE1 : LPI_TEST_TO_VPE0;
> +	u64 expected_hwirq = gicv5_lpi_hwirq(expected_lpi);
> +	u32 hwirq;
> +	u64 ia;
> +
> +	ia = gicr_insn(CDIA);
> +	if (!GICV5_GICR_CDIA_VALID(ia))
> +		return;
> +
> +	gsb_ack();
> +	isb();
> +
> +	hwirq = FIELD_GET(GICV5_GICR_CDIA_INTID, ia);
> +	GUEST_ASSERT_EQ(hwirq, expected_hwirq);
> +
> +	gic_insn(hwirq, CDDI);
> +	gic_insn(0, CDEOI);

[Severity: Medium]
Will this lead to misencoded instructions?

The system instruction GIC CDEOI requires the fixed register XZR, but is
emitted using the gic_insn() macro which expands to write_sysreg_s() using a
compiler constraint instead of a hardcoded register.

If the compiler selects a general-purpose register other than XZR, this could
result in CONSTRAINED UNPREDICTABLE behavior. Should this instruction use an
inline assembly block that explicitly hardcodes the exact register in the
instruction string?

> +
> +	if (vcpu_id) {
> +		gicv5_send_lpi(LPI_TEST_TO_VPE0);
> +		GUEST_SYNC(GUEST_CMD_LPI_REPLIED);
> +		while (1)
> +			wfi();
> +	}
> +
> +	GUEST_DONE();
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260807111159.429128-1-sascha.bischoff@arm.com?part=47