From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mta1.migadu.com (out-26.mta1.migadu.com [95.215.58.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29E47415F3C for ; Mon, 7 Sep 2026 07:01:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.26 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788764513; cv=none; b=kFaqfYq8Etlm+VVUrs2ZkAJ+46St7jcUap/ua0jb5NlI831/3euS+x3HU0T0mM+WoZucywklpan7dd0goQIbFcot8EMQFyAsxIq6JStPQCshJD8+n3UHn7UOVyR2wvik6zmXY28yeK4ZczNOyWYnvftB6F2O7DwbbJLyXH5XOO8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788764513; c=relaxed/simple; bh=U/axjWQAfQSFNwOk+gQLgXnGQvfOgoP7MHtzfv1LyiQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MXWjJg9OqRh1j4iMmrkWztfPjKfY/n5nb8cHLGptip4wTXPHVj5MjZLwQwYhcIRwbTcxs5B1UAO9KIYkMI6UmPuSlAFcihHCy74+Ov9+JxFA6NaWvJBV+RESFvjxb+ucG+u6Er+IHx6xTtAZe+z38MbzpoWP+Mb5Jgy4YitnKvc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=WGMKie+k; arc=none smtp.client-ip=95.215.58.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="WGMKie+k" X-Envelope-To: kvmarm@lists.linux.dev DKIM-Signature: a=rsa-sha256; bh=U/axjWQAfQSFNwOk+gQLgXnGQvfOgoP7MHtzfv1LyiQ=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1788764498; v=1; x=1789369298; b=WGMKie+k9l0m1QyQdxO2azYFgoj8SFmFgBdU0oZioZ6vybLS2TXoEZktugpuEn6L5bof695P 0bPT1V0dTTa09Fujr/E2StjZF2M7u0b3DTLPJiYg1rlrthNoH3UsiwRcjn0jcNhjQdmI6cTNqlO jZGOKmHPyJwD10igHXTEa2AE= X-Envelope-To: kvmarm@lists.linux.dev Received: by smtp.migadu.com with ESMTPS id d54cb9ebe02a4a1c; Mon, 07 Sep 2026 07:01:38 +0000 X-Mizu-Trace-ID: d54cb9ebe02a4a1c X-Migadu-Flow: FLOW_OUT From: Fuad Tabba To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Vincent Donnefort , Quentin Perret , Fuad Tabba Subject: [PATCH v2 13/17] KVM: arm64: Pend a protected guest's SError with HCR_EL2.VSE only Date: Mon, 7 Sep 2026 07:59:58 +0100 Message-Id: <20260907070002.3333525-14-fuad.tabba@linux.dev> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260907070002.3333525-1-fuad.tabba@linux.dev> References: <20260907070002.3333525-1-fuad.tabba@linux.dev> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit kvm_inject_serror_esr() emulates the exception entry when serror_is_masked() reads PSTATE.A clear, but the host has no view of a protected guest's PSTATE.A, and an emulated entry never reaches the guest: the SError is lost. Set VSE instead and let the guest's own PSTATE.A mask it. Signed-off-by: Fuad Tabba --- arch/arm64/kvm/inject_fault.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index d6c4fc16f8795..b88098a7e756c 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -378,8 +378,11 @@ int kvm_inject_serror_esr(struct kvm_vcpu *vcpu, u64 esr) * * As we're emulating the SError injection we need to explicitly populate * ESR_ELx.EC because hardware will not do it on our behalf. + * + * The host does not see a protected guest's PSTATE.A: leave the + * vSError to HCR_EL2.VSE below, which the guest masks itself. */ - if (!serror_is_masked(vcpu)) { + if (!vcpu_is_protected(vcpu) && !serror_is_masked(vcpu)) { pend_serror_exception(vcpu); esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SERROR) | ESR_ELx_IL; vcpu_write_sys_reg(vcpu, esr, exception_esr_elx(vcpu)); -- 2.39.5