From: sashiko-bot@kernel.org
To: "Wei-Lin Chang" <weilin.chang@arm.com>
Cc: kvmarm@lists.linux.dev, "Marc Zyngier" <maz@kernel.org>,
"Oliver Upton" <oupton@kernel.org>
Subject: Re: [PATCH v1 2/3] arm64: sysreg: Add TCR_EL2 to sysreg infrastructure
Date: Wed, 09 Sep 2026 22:38:10 +0000 [thread overview]
Message-ID: <20260909223811.386071F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260909222015.3046432-3-weilin.chang@arm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Declarative update to TCR_EL2 regenerates the TCR_EL2_RES1 aggregate mask which is consumed by C initialization, requiring confirmation of robustness to future value changes.
--
commit 522a184d95be9c0f88cc6fb418668546ef83e3e4
Author: Wei-Lin Chang <weilin.chang@arm.com>
arm64: sysreg: Add TCR_EL2 to sysreg infrastructure
Convert TCR_EL2 to the sysreg infrastructure with data extracted from
Registers.json of the BSD licenced AARCHMRS
(AARCHMRS_OPENSOURCE_A_profile_FAT-2026-06).
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 94bf065c8ac71..8d89f34580bac 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
[ ... ]
> +Sysreg TCR_EL2 3 4 2 0 2
[ ... ]
> +Field 33 MTX
> +Field 32 DS
> +Res1 31
> +Field 30 TCMA
> +Field 29 TBID
> +Field 28 HWU62
> +Field 27 HWU61
> +Field 26 HWU60
> +Field 25 HWU59
> +Field 24 HPD
> +Res1 23
> +Field 22 HD
[Severity: Medium]
This isn't a bug, but this declarative update regenerates the TCR_EL2_RES1
aggregate mask. Are the C initialization consumers of this mask robust to its
value silently changing if a future .sysreg patch adds or removes a Res1 bit?
For example, the generated mask is OR'd into the initial EL2 register value:
arch/arm64/kvm/arm.c:cpu_prepare_hyp_mode() {
...
tcr |= TCR_EL2_RES1 | FIELD_PREP(TCR_EL2_PS_MASK, ips);
...
}
It is also used to initialize the guest emulation reset state in:
arch/arm64/kvm/sys_regs.c:sys_reg_descs[] = {
...
EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
...
}
Because the generator's contract is to reflect global architectural truth, a
future edit that reclassifies a bit as Res1 will silently change the value of
TCR_EL2_RES1 without triggering a compiler or CI warning. Could you confirm
that these consumers do not rely on the previous static semantic value of the
mask?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260909222015.3046432-1-weilin.chang@arm.com?part=2
next prev parent reply other threads:[~2026-09-09 22:38 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 22:20 [PATCH v1 0/3] KVM: arm64: Properly advertise !FEAT_LPA2 for NV Wei-Lin Chang
2026-09-09 22:20 ` [PATCH v1 1/3] KVM: arm64: nv: Don't advertise FEAT_LPA2 for guest stage-1 Wei-Lin Chang
2026-09-09 22:44 ` sashiko-bot
2026-09-10 10:56 ` Wei-Lin Chang
2026-09-11 8:22 ` Marc Zyngier
2026-09-11 9:08 ` Marc Zyngier
2026-09-09 22:20 ` [PATCH v1 2/3] arm64: sysreg: Add TCR_EL2 to sysreg infrastructure Wei-Lin Chang
2026-09-09 22:38 ` sashiko-bot [this message]
2026-09-10 10:58 ` Wei-Lin Chang
2026-09-11 8:45 ` Marc Zyngier
2026-09-10 11:54 ` Mark Brown
2026-09-09 22:20 ` [PATCH v1 3/3] KVM: arm64: Convert TCR_EL2 to config-driven sanitisation Wei-Lin Chang
2026-09-11 9:04 ` Marc Zyngier
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