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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-145ad9e097fsm1289075c88.13.2026.09.24.14.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 14:38:24 -0700 (PDT) Date: Thu, 24 Sep 2026 14:38:21 -0700 From: Jonathan Cameron To: Suzuki K Poulose Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, maz@kernel.org, will@kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, steven.price@arm.com, aneesh.kumar@kernel.org, oupton@kernel.org, gshan@redhat.com, joey.gouly@arm.com, tabba@google.com, yuzenghui@huawei.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, sdonthineni@nvidia.com, alpergun@google.com, fj0570is@fujitsu.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org, enju.kohei@fujitsu.com, sudeep.holla@arm.com Subject: Re: [PATCH v19 6/7] firmware: arm_rmm: Ensure the RMM has GPT entries for memory Message-ID: <20260924143821.00003491@oss.qualcomm.com> In-Reply-To: <20260924135201.850038-7-suzuki.poulose@arm.com> References: <20260924135201.850038-1-suzuki.poulose@arm.com> <20260924135201.850038-7-suzuki.poulose@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDA4OCBTYWx0ZWRfXxuValjJvRwBz wTyPmnAjgGMW3XYbagrCB2BTp+pYRP5hrTvy3LSVgSkD50RVG/lo3ze7XfvAUNQjGu2LYNwI4UB gb74xiIbR07Tbrt0mgjuFAkHyZRUHqfDQRcWqDpsIo/fAZGwApajJXHsB1PaeSqS4POQhOvka4y J81r9MkjI9p8gF2aEOrZKWfCHkyq6qDEL1EHYVQIrBwE087MQibMZvZoky6qPv5vfRm+vDUonG9 k5tmmqJf1OUd7BkDIFDcW+tj4gri4N/YKe6BVE5YZCcUsIKdb3LV2PVBtV6xNKncue/DEpXZnuS SMXVlWrc/gf73A/RIEMT9fwbSPG6nplUcnICVIZjDjuIC2YJGz5XgB76upJIDMhQkVyi00z+XZG Uycy8In98sQMfb2P94WfY0l2PVsLjnY2vmyL/8nhYHcXDrQrb0q8vR1tWSGl+6ycon7moNoDJjO Gn7+EoCHv2MgOow05bQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDA4OCBTYWx0ZWRfX+s6+hOoRQ3WN n7autPlFTzfs0BjcLr7xMUbgzAyiXV+Fk+s+DPZC4N54milAJW0YJNq4Qd1lXH3sJwamBpoc9lO 4UjoYy5FUeC2zfJcQz3Wdgw6QrVu9p0= X-Proofpoint-GUID: 5NKiN94vU4mzV2ILOa0VTP5fq2IoNz4U X-Proofpoint-ORIG-GUID: 5NKiN94vU4mzV2ILOa0VTP5fq2IoNz4U X-Authority-Analysis: v=2.4 cv=EJWTQFZC c=1 sm=1 tr=0 ts=6ab59854 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=8d2wJ0fT7bLMqeC6Z9UA:9 a=CjuIK1q_8ugA:10 a=Fk4IpSoW4aLDllm1B1p-:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240088 On Thu, 24 Sep 2026 14:52:00 +0100 Suzuki K Poulose wrote: > From: Steven Price > > The RMM maintains the state of all the granules in the system to make > sure that the host is abiding by the rules. This state can be maintained > at different granularity, per page (TRACKING_FINE) or per region > (TRACKING_COARSE or TRACKING_INTERMEDIATE). The region size depends on the > underlying "RMI_GRANULE_SIZE". For a "coarse"/"intermediate" region, > all pages in the region must be of the same state, this implies we need to > have "fine" tracking for DRAM, so that we can delegate individual pages. > > For now we only support a statically carved out memory for tracking > granules for the "fine" regions. This can be extended in the future to > allow modifying the tracking granularity and remove the need for a > static allocation by the firmware. > > Similarly, the firmware may create L0 GPT entries describing the total > address space. But if we change the "PAS" (Physical Address Space) of a > granule, then the firmware may need to create L1 tables to track the PAS > at a finer granularity. Linux therefore checks if the platform firmware > manages the PAR region. i.e., the firmware is in charge of managing the > L1 GPTs (creation and the required memory for the GPT tables - via static > carveouts) without host intervention. Support for dynamic GPT creation by > the host will be added later. > > If the firmware requires us to manage the tracking or GPT memory, > deactivate the RMM and reclaim any memory donated at RMM activation. > > Apply the same checks when hotplugged memory is brought online. > > Signed-off-by: Steven Price > [ Switch to RMI_GPT_L1_INFO for checking GPTs and deactivate RMM ] > Co-developed-by: Suzuki K Poulose > Signed-off-by: Suzuki K Poulose A few trivial comments. Either way on those Reviewed-by: Jonathan Cameron > --- > drivers/firmware/arm_rmm/rmi.c | 218 ++++++++++++++++++++++++++++++++- > include/linux/arm-rmi-cmds.h | 2 + > 2 files changed, 219 insertions(+), 1 deletion(-) > > diff --git a/drivers/firmware/arm_rmm/rmi.c b/drivers/firmware/arm_rmm/rmi.c > index 0859f256e192b..1a8f3debd844a 100644 > --- a/drivers/firmware/arm_rmm/rmi.c > +++ b/drivers/firmware/arm_rmm/rmi.c > + > +/* > + * rmi_gpt_info - Query the GPT info for the given PAR. > + * @start: Base of the physical address region > + * @end: Top of the physical address region > + * @out_top: Top of the physical address region for which > + * the GPT @out_gpt_par_state is valid wrap to 80. > + * @out_gpt_par_state: State of the GPT covered by [start, out_top) > + */ > +static long rmi_gpt_info(unsigned long start, unsigned long end, > + unsigned long *out_top, > + unsigned long *out_gpt_par_state) > +{ > + struct arm_smccc_1_2_regs regs = { > + SMC_RMI_GPT_INFO, start, end, > + }; > + > + rmi_smccc_invoke(®s); > + if (regs.a0 != RMI_SUCCESS) > + return regs.a0; > + > + if (out_top) > + *out_top = regs.a1; > + if (out_gpt_par_state) > + *out_gpt_par_state = regs.a2; > + > + return RMI_SUCCESS; > +} > + > +/* > + * We do not support creating L1 GPTs yet. So, make sure that > + * all the regions are managed by the firmware. Wrap to 80 chars. Not relevant to this patch, but when are you thinking we will support that? > + */ > +static int rmi_verify_gpt_firmware_managed(phys_addr_t start, phys_addr_t end) > +{ > + unsigned long l0gpt_sz; > + unsigned long next, par_state; > + > + l0gpt_sz = 1UL << (30 + FIELD_GET(RMI_FEATURE_REGISTER_1_L0GPTSZ, > + rmi_feat_reg(1))); > + start = ALIGN_DOWN(start, l0gpt_sz); > + end = ALIGN(end, l0gpt_sz); > + > + while (start < end) { > + long ret = rmi_gpt_info(start, end, &next, &par_state); > + > + if (ret != RMI_SUCCESS) > + return -ENOMEM; > + > + if (WARN_ON(next <= start)) > + return -ENXIO; > + > + if (par_state != RMI_GPT_PAR_PLAT) { > + pr_err("GPT for the region is not managed by firmware %llx-%lx\n", > + start, next); > + return -ENOMEM; > + } > + start = next; > + } > + > + return 0; > +} > + > +static int rmi_init_metadata(void) > +{ > + phys_addr_t start, end; > + struct memblock_region *r; > + > + for_each_mem_region(r) { > + int ret; > + > + /* Firmware-reserved NOMAP regions are not usable system RAM */ > + if (memblock_is_nomap(r)) > + continue; > + > + start = PAGE_ALIGN(r->base); > + end = PAGE_ALIGN_DOWN(r->base + r->size); Add a comment on why rounding down. Doe we expect that to ever be relevant? > + /* Too small ? */ > + if (start >= end) > + continue; > + > + ret = rmi_prepare_memory(start, end); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > static int __init arm64_init_rmi(void) > { > int ret; > @@ -843,9 +1049,19 @@ static int __init arm64_init_rmi(void) > if (ret) { > pr_err("RMM activate failed (%d)\n", ret); > ret = ret < 0 ? ret : -ENXIO; > + return ret; > } > > - return ret; > + ret = rmi_init_memory(); > + if (ret) { > + /* Deactivate the RMM */ > + WARN_ON(rmi_sro_memxfer_cmd(sro, GFP_KERNEL, SMC_RMI_RMM_DEACTIVATE)); > + return ret; > + } > + > + arm64_rmi_is_available = true; > + pr_info("RMI configured\n"); Blank line nice for the eye to spot the return. > + return 0; > }