From: Oliver Upton <oupton@kernel.org>
To: kvmarm@lists.linux.dev
Cc: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Wei-Lin Chang <weilin.chang@arm.com>,
Steffen Eiden <seiden@linux.ibm.com>,
Fuad Tabba <fuad.tabba@linux.dev>,
Mark Brown <broonie@kernel.org>, Oliver Upton <oupton@kernel.org>
Subject: [PATCH v3 2/5] arm64: sysreg: Add TCR_EL2 to sysreg infrastructure
Date: Thu, 29 Oct 2026 15:37:29 -0700 [thread overview]
Message-ID: <20261029223732.103785-3-oupton@kernel.org> (raw)
In-Reply-To: <20261029223732.103785-1-oupton@kernel.org>
From: Wei-Lin Chang <weilin.chang@arm.com>
Convert TCR_EL2 to the sysreg infrastructure with data extracted from
Registers.json of the BSD licenced AARCHMRS
(AARCHMRS_OPENSOURCE_A_profile_FAT-2026-06).
There are two formats of TCR_EL2 based on whether the effective value of
HCR_EL2.E2H is 0 or 1. For the E2H == 1 case, prefix the macros with
"VHE_". For the E2H == 0 case, the macros are left unprefixed.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
Signed-off-by: Oliver Upton <oupton@kernel.org>
---
arch/arm64/include/asm/kvm_arm.h | 13 ----
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 125 +++++++++++++++++++++++++++++++
3 files changed, 125 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index ba0062849be9..3e1c9e31028e 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -45,19 +45,6 @@
#define MPAMHCR_HOST_FLAGS 0
/* TCR_EL2 Registers bits */
-#define TCR_EL2_DS (1UL << 32)
-#define TCR_EL2_RES1 ((1U << 31) | (1 << 23))
-#define TCR_EL2_HPD (1 << 24)
-#define TCR_EL2_HA (1 << 21)
-#define TCR_EL2_TBI (1 << 20)
-#define TCR_EL2_PS_SHIFT 16
-#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
-#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
-#define TCR_EL2_TG0_MASK TCR_TG0_MASK
-#define TCR_EL2_SH0_MASK TCR_SH0_MASK
-#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
-#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
-#define TCR_EL2_T0SZ_MASK 0x3f
#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index aa65603455a2..fee89cd667d9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -519,7 +519,6 @@
#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
#define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
-#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 893b5f9df575..bbe32dee55f9 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -5612,6 +5612,131 @@ Res0 6
Field 5:0 T0SZ
EndSysreg
+Sysreg TCR_EL2 3 4 2 0 2
+Prefix VHE
+Res0 63:62
+Field 61 MTX1
+Field 60 MTX0
+Field 59 DS
+Field 58 TCMA1
+Field 57 TCMA0
+Field 56 E0PD1
+Field 55 E0PD0
+Field 54 NFD1
+Field 53 NFD0
+Field 52 TBID1
+Field 51 TBID0
+Field 50 HWU162
+Field 49 HWU161
+Field 48 HWU160
+Field 47 HWU159
+Field 46 HWU062
+Field 45 HWU061
+Field 44 HWU060
+Field 43 HWU059
+Field 42 HPD1
+Field 41 HPD0
+Field 40 HD
+Field 39 HA
+Field 38 TBI1
+Field 37 TBI0
+Field 36 AS
+Res0 35
+Field 34:32 IPS
+Enum 31:30 TG1
+ 0b01 16K
+ 0b10 4K
+ 0b11 64K
+EndEnum
+Enum 29:28 SH1
+ 0b00 NONE
+ 0b10 OUTER
+ 0b11 INNER
+EndEnum
+Enum 27:26 ORGN1
+ 0b00 NC
+ 0b01 WBWA
+ 0b10 WT
+ 0b11 WBnWA
+EndEnum
+Enum 25:24 IRGN1
+ 0b00 NC
+ 0b01 WBWA
+ 0b10 WT
+ 0b11 WBnWA
+EndEnum
+Field 23 EPD1
+Field 22 A1
+Field 21:16 T1SZ
+Enum 15:14 TG0
+ 0b00 4K
+ 0b01 64K
+ 0b10 16K
+EndEnum
+Enum 13:12 SH0
+ 0b00 NONE
+ 0b10 OUTER
+ 0b11 INNER
+EndEnum
+Enum 11:10 ORGN0
+ 0b00 NC
+ 0b01 WBWA
+ 0b10 WT
+ 0b11 WBnWA
+EndEnum
+Enum 9:8 IRGN0
+ 0b00 NC
+ 0b01 WBWA
+ 0b10 WT
+ 0b11 WBnWA
+EndEnum
+Field 7 EPD0
+Res0 6
+Field 5:0 T0SZ
+EndPrefix
+Res0 63:34
+Field 33 MTX
+Field 32 DS
+Res1 31
+Field 30 TCMA
+Field 29 TBID
+Field 28 HWU62
+Field 27 HWU61
+Field 26 HWU60
+Field 25 HWU59
+Field 24 HPD
+Res1 23
+Field 22 HD
+Field 21 HA
+Field 20 TBI
+Res0 19
+Field 18:16 PS
+Enum 15:14 TG0
+ 0b00 4K
+ 0b01 64K
+ 0b10 16K
+EndEnum
+Enum 13:12 SH0
+ 0b00 NONE
+ 0b10 OUTER
+ 0b11 INNER
+EndEnum
+Enum 11:10 ORGN0
+ 0b00 NC
+ 0b01 WBWA
+ 0b10 WT
+ 0b11 WBnWA
+EndEnum
+Enum 9:8 IRGN0
+ 0b00 NC
+ 0b01 WBWA
+ 0b10 WT
+ 0b11 WBnWA
+EndEnum
+Res0 7:6
+Field 5:0 T0SZ
+EndSysreg
+
Sysreg TCR_EL12 3 5 2 0 2
Mapping TCR_EL1
EndSysreg
--
2.47.3
next prev parent reply other threads:[~2026-10-29 22:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 22:37 [PATCH v3 0/5] KVM: arm64: TCR_EL2 fixes, FEAT_LPA2=NI for NV Oliver Upton
2026-10-29 22:37 ` [PATCH v3 1/5] KVM: arm64: nv: Don't advertise FEAT_LPA2 for guest stage-1 Oliver Upton
2026-10-29 22:37 ` Oliver Upton [this message]
2026-10-29 22:37 ` [PATCH v3 3/5] KVM: arm64: Reset TCR_EL2 according to guest's E2H mode Oliver Upton
2026-10-29 22:37 ` [PATCH v3 4/5] KVM: arm64: Convert TCR_EL2 to config-driven sanitisation Oliver Upton
2026-10-30 1:26 ` Wei-Lin Chang
2026-10-29 22:37 ` [PATCH v3 5/5] KVM: arm64: nv: Correctly compute the effective TCR_EL1 for nVHE TCR_EL2 Oliver Upton
2026-10-30 1:13 ` Wei-Lin Chang
2026-10-30 11:03 ` [PATCH v3 0/5] KVM: arm64: TCR_EL2 fixes, FEAT_LPA2=NI for NV Fuad Tabba
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