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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd9180f2sm184056535e9.19.2024.11.04.06.45.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Nov 2024 06:45:16 -0800 (PST) Message-ID: <24ca0278-5018-41e3-a097-ac560a16f8fa@redhat.com> Date: Mon, 4 Nov 2024 15:45:13 +0100 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: eric.auger@redhat.com Subject: Re: [RFC 21/21] arm/cpu-features: Document custom vcpu model To: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Cornelia Huck Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, abologna@redhat.com, jdenemar@redhat.com, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com References: <20241025101959.601048-1-eric.auger@redhat.com> <20241025101959.601048-22-eric.auger@redhat.com> <0700af51-a1a6-4b11-a4bf-0eaf6e279c6d@redhat.com> <87y128nrfr.fsf@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi On 10/28/24 17:09, Daniel P. Berrangé wrote: > On Mon, Oct 28, 2024 at 05:05:44PM +0100, Cornelia Huck wrote: >> On Fri, Oct 25 2024, Daniel P. Berrangé wrote: >> >>> On Fri, Oct 25, 2024 at 03:28:35PM +0200, Eric Auger wrote: >>>> Hi Daniel, >>>> >>>> On 10/25/24 15:13, Daniel P. Berrangé wrote: >>>>> On Fri, Oct 25, 2024 at 12:17:40PM +0200, Eric Auger wrote: >>>>>> From: Cornelia Huck >>>>>> >>>>>> Add some documentation for the custom model. >>>>>> >>>>>> Signed-off-by: Eric Auger >>>>>> Signed-off-by: Cornelia Huck >>>>>> --- >>>>>> docs/system/arm/cpu-features.rst | 55 +++++++++++++++++++++++++++----- >>>>>> 1 file changed, 47 insertions(+), 8 deletions(-) >>>>>> @@ -167,6 +196,16 @@ disabling many SVE vector lengths would be quite verbose, the ``sve`` CPU >>>>>> properties have special semantics (see "SVE CPU Property Parsing >>>>>> Semantics"). >>>>>> >>>>>> +The ``custom`` CPU model needs to be configured via individual ID register >>>>>> +field properties, for example:: >>>>>> + >>>>>> + $ qemu-system-aarch64 -M virt -cpu custom,SYSREG_ID_AA64ISAR0_EL1_DP=0x0 >>>>>> + >>>>>> +This forces ID_AA64ISAR0_EL1 DP field to 0. >>>>> What is the "baseline" featureset implied by 'custom' ? >>>> there is no baseline at the moment. By default this is a host >>>> passthrough model. >>> Why do we need to create "custom" at all, as opposed to just letting >>> users toggle features on "-cpu host" ? >> We could consolidate that to the current "host" model, once we figure >> out how to handle the currently already existing properties. Models >> based on the different architecture extensions would probably be more >> useable in the long run; maybe "custom" has a place for testing. > If you can set the features against "host", then any testing could > be done with "host" surely, making 'custom' pointless ? Yeah I do agree that we may not need to introduce this "custom" model bus just enhance the custom host model with the capability to tweek some features. For instance we have the case where migration between 2 Ampere systems fails with host model but if you tweek 1 field in CTR_EL0 it passes. So I think in itself this modality can be useful. Same for debug/test purpose. As mentionned in the cover letter the number of writable ID regs continue to grow and this enhanced host model gives flexibility to test new support and may provide enhanced debug capabilities for migration (getting a straight understanding of which ID reg field(s) causes the migration failure could be helpful I think) Thanks Eric > > With regards, > Daniel