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Thu, 05 Nov 2020 11:08:41 +0000 MIME-Version: 1.0 Date: Thu, 05 Nov 2020 11:08:38 +0000 From: Marc Zyngier To: David Brazdil Subject: Re: [RFC PATCH 12/26] kvm: arm64: Add SMC handler in nVHE EL2 In-Reply-To: <20201104183630.27513-13-dbrazdil@google.com> References: <20201104183630.27513-1-dbrazdil@google.com> <20201104183630.27513-13-dbrazdil@google.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <35d054aa819034831a04aa3332aceec2@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: dbrazdil@google.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will@kernel.org, dennis@kernel.org, tj@kernel.org, cl@linux.com, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, qperret@google.com, ascull@google.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: Lorenzo Pieralisi , kernel-team@android.com, Catalin Marinas , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tejun Heo , Dennis Zhou , Christoph Lameter , Will Deacon , kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 2020-11-04 18:36, David Brazdil wrote: > Add handler of host SMCs in KVM nVHE trap handler. Forward all SMCs to > EL3 and propagate the result back to EL1. This is done in preparation > for validating host SMCs. > > Signed-off-by: David Brazdil > --- > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 36 ++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c > b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > index 19332c20fcde..fffc2dc09a1f 100644 > --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > @@ -106,6 +106,38 @@ static void handle_host_hcall(struct > kvm_cpu_context *host_ctxt) > host_ctxt->regs.regs[1] = ret; > } > > +static void skip_host_instruction(void) > +{ > + write_sysreg_el2(read_sysreg_el2(SYS_ELR) + 4, SYS_ELR); > +} > + > +static void forward_host_smc(struct kvm_cpu_context *host_ctxt) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_1_1_smc(host_ctxt->regs.regs[0], host_ctxt->regs.regs[1], > + host_ctxt->regs.regs[2], host_ctxt->regs.regs[3], > + host_ctxt->regs.regs[4], host_ctxt->regs.regs[5], > + host_ctxt->regs.regs[6], host_ctxt->regs.regs[7], > + &res); > + host_ctxt->regs.regs[0] = res.a0; > + host_ctxt->regs.regs[1] = res.a1; > + host_ctxt->regs.regs[2] = res.a2; > + host_ctxt->regs.regs[3] = res.a3; > +} > + > +static void handle_host_smc(struct kvm_cpu_context *host_ctxt) > +{ > + /* > + * Unlike HVC, the return address of an SMC is the instruction's PC. > + * Move the return address past the instruction. > + */ > + skip_host_instruction(); > + > + /* Forward SMC not handled in EL2 to EL3. */ > + forward_host_smc(host_ctxt); > +} > + > void handle_trap(struct kvm_cpu_context *host_ctxt) > { > u64 esr = read_sysreg_el2(SYS_ESR); > @@ -114,6 +146,10 @@ void handle_trap(struct kvm_cpu_context > *host_ctxt) > case ESR_ELx_EC_HVC64: > handle_host_hcall(host_ctxt); > break; > + case ESR_ELx_EC_SMC32: How is that even possible? Host EL1 is strictly 64bit, so SMC32 cannot occur. > + case ESR_ELx_EC_SMC64: > + handle_host_smc(host_ctxt); > + break; > default: > hyp_panic(); > } Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm