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Sun, 31 May 2020 13:44:40 +0100 MIME-Version: 1.0 Date: Sun, 31 May 2020 13:44:40 +0100 From: Marc Zyngier To: Paolo Bonzini Subject: Re: [PATCH RFCv2 9/9] arm64: Support async page fault In-Reply-To: References: <20200508032919.52147-1-gshan@redhat.com> <20200508032919.52147-10-gshan@redhat.com> <81adf013-3de7-23e6-7648-8aec821b033c@redhat.com> <8ab64c6a-582b-691d-79ab-21cdc0455cd3@redhat.com> <6a4a82a4-af01-98c2-c854-9199f55f7bd3@redhat.com> <6965aaf641a23fab64fbe2ceeb790272@kernel.org> User-Agent: Roundcube Webmail/1.4.4 Message-ID: <4337cca152df47c93d96e092189a0e36@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: pbonzini@redhat.com, gshan@redhat.com, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, shan.gavin@gmail.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: catalin.marinas@arm.com, linux-kernel@vger.kernel.org, shan.gavin@gmail.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 2020-05-29 12:11, Paolo Bonzini wrote: > On 29/05/20 11:41, Marc Zyngier wrote: >>>> >>>> >>>> For x86 the advantage is that the processor can take care of raising >>>> the >>>> stage2 page fault in the guest, so it's faster. >>>> >>> I think there might be too much overhead if the page can be populated >>> quickly by host. For example, it's fast to populate the pages if >>> swapin >>> isn't involved. > > Those would still be handled by the host. Only those that are not > present in the host (which you can see through the MMU notifier) would > be routed to the guest. You can do things differently between "not > present fault because the page table does not exist" and "not present > fault because the page is missing in the host". > >>> If I'm correct enough, it seems arm64 doesn't have similar mechanism, >>> routing stage2 page fault to guest. >> >> Indeed, this isn't a thing on arm64. Exception caused by a S2 fault >> are >> always routed to EL2. > > Is there an ARM-approved way to reuse the S2 fault syndromes to detect > async page faults? It would mean being able to set an ESR_EL2 register value into ESR_EL1, and there is nothing in the architecture that would allow that, with the exception of nested virt: a VHE guest hypervisor running at EL1 must be able to observe S2 faults for its own S2, as synthesized by the host hypervisor. The trouble is that: - there is so far no commercially available CPU supporting NV - even if you could get hold of such a machine, there is no guarantee that such "EL2 syndrome at EL1" is valid outside of the nested context - this doesn't solve the issue for non-NV CPUs anyway > (By the way, another "modern" use for async page faults is for postcopy > live migration). Right. That's definitely a more interesting version of "swap-in". M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm