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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4327d698144sm163984475e9.39.2024.11.04.09.07.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Nov 2024 09:07:23 -0800 (PST) Message-ID: <48637795-14b9-4b0c-9fb5-46b387be4fd0@redhat.com> Date: Mon, 4 Nov 2024 18:07:21 +0100 Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: eric.auger@redhat.com Subject: Re: [RFC 21/21] arm/cpu-features: Document custom vcpu model To: Peter Maydell Cc: Kashyap Chamarthy , eric.auger.pro@gmail.com, cohuck@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com References: <20241025101959.601048-1-eric.auger@redhat.com> <20241025101959.601048-22-eric.auger@redhat.com> <52690aae-55b6-47d5-a308-dd75475f8377@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Peter, On 11/4/24 17:30, Peter Maydell wrote: > On Mon, 4 Nov 2024 at 15:34, Eric Auger wrote: >> Hi Kashyap, >> >> On 10/28/24 22:17, Kashyap Chamarthy wrote: >>> On Fri, Oct 25, 2024 at 12:17:40PM +0200, Eric Auger wrote: >>>> From: Cornelia Huck >>>> >>>> Add some documentation for the custom model. >>>> >>>> Signed-off-by: Eric Auger >>>> Signed-off-by: Cornelia Huck >>>> --- >>>> docs/system/arm/cpu-features.rst | 55 +++++++++++++++++++++++++++----- >>>> 1 file changed, 47 insertions(+), 8 deletions(-) >>>> >>>> diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst >>>> index a5fb929243..962a2c6c26 100644 >>>> --- a/docs/system/arm/cpu-features.rst >>>> +++ b/docs/system/arm/cpu-features.rst >>>> @@ -2,7 +2,10 @@ Arm CPU Features >>> [...] >>> >>>> +Using the ``host`` type means the guest is provided all the same CPU >>>> +features as the host CPU type has. And, for this reason, the ``host`` >>>> +CPU type should enable all CPU features that the host has by default. >>>> + >>>> +In case some features need to be hidden to the guest, ``custom`` model >>>> +shall be used instead. This is especially useful for migration purpose. >>>> + >>>> +The ``custom`` CPU model generally is the better choice if you want more >>>> +flexibility or stability across different machines or with different kernel >>>> +versions. >>> Does "more flexibility or stability across different machines" also >>> imply "live migration compatiblity across host CPUs"? >> yes that's the goal >>>> However, even the ``custom`` CPU model will not allow configuring >>>> +an arbitrary set of features; the ID registers must describe a subset of the >>>> +host's features, and all differences to the host's configuration must actually >>>> +be supported by the kernel to be deconfigured. >>> [...] >>> >>>> +The ``custom`` CPU model needs to be configured via individual ID register >>>> +field properties, for example:: >>>> + >>>> + $ qemu-system-aarch64 -M virt -cpu custom,SYSREG_ID_AA64ISAR0_EL1_DP=0x0 >>> If possible, it would be really helpful (and user-friendly) to be able >>> to specify the CPU feature names as you see under /proc/cpuinfo, and be >>> able to turn the flags on or off: >>> >>> -M virt -cpu franken,rndr=on,ts=on,fhm=off >>> >>> (... instead of specifying long system register IDs that groups together >>> a bunch of CPU features. If I understand it correctly, the register >>> "ID_AA64ISAR0_EL1" maps to a set of visible features listed here: >>> https://docs.kernel.org/arch/arm64/cpu-feature-registers.html) >> Not all the writable ID regs are visible through the above technique. >> But indeed I think we converged on the idea to use higher level feature >> names than ID reg field values. >> However we need to study the feasibility and mappings between those high >> level features and ID reg field values. >> The cons is that we need to describe this mapping manually. Besides >> being cumbersome this is also error prone. > You might be interested in "Arm Architecture Features" on > https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads > which includes a 1.8MB Features.json which is a machine > readable version of the "what are the features and their > dependencies and ID registers and so on" information. thank you for the link. > > But note that (a) it is alpha quality and (b) I am not personally > going to try to interpret what might be reasonable to do with it > based on the legal notice attached to it: that's a matter for > you and your lawyer ;-) Thank you for the notice. This may be similar to the ARM xml mentioned by Marc... Eric > > -- PMM >