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Thu, 3 Sep 2020 05:09:55 +0000 (UTC) Received: from [10.64.54.159] (vpn2-54-159.bne.redhat.com [10.64.54.159]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2B0D8196F3; Thu, 3 Sep 2020 05:09:52 +0000 (UTC) Subject: Re: [PATCH v3 21/21] KVM: arm64: Don't constrain maximum IPA size based on host configuration To: Will Deacon , kvmarm@lists.cs.columbia.edu References: <20200825093953.26493-1-will@kernel.org> <20200825093953.26493-22-will@kernel.org> From: Gavin Shan Message-ID: <492420d8-91d7-a258-cf8a-17da29719d86@redhat.com> Date: Thu, 3 Sep 2020 15:09:50 +1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20200825093953.26493-22-will@kernel.org> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=gshan@redhat.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Language: en-US Cc: Marc Zyngier , Catalin Marinas , kernel-team@android.com, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list Reply-To: Gavin Shan List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Will, On 8/25/20 7:39 PM, Will Deacon wrote: > Now that the guest stage-2 page-tables are managed independently from > the host stage-1 page-tables, we can avoid constraining the IPA size > based on the host and instead limit it only based on the PARange field > of the ID_AA64MMFR0 register. > > Cc: Marc Zyngier > Cc: Quentin Perret > Signed-off-by: Will Deacon > --- > arch/arm64/kvm/reset.c | 38 +++++--------------------------------- > 1 file changed, 5 insertions(+), 33 deletions(-) > Reviewed-by: Gavin Shan > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > index ee33875c5c2a..471ee9234e40 100644 > --- a/arch/arm64/kvm/reset.c > +++ b/arch/arm64/kvm/reset.c > @@ -339,7 +339,7 @@ u32 get_kvm_ipa_limit(void) > > int kvm_set_ipa_limit(void) > { > - unsigned int ipa_max, pa_max, va_max, parange, tgran_2; > + unsigned int parange, tgran_2; > u64 mmfr0; > > mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); > @@ -376,38 +376,10 @@ int kvm_set_ipa_limit(void) > break; > } > > - pa_max = id_aa64mmfr0_parange_to_phys_shift(parange); > - > - /* Clamp the IPA limit to the PA size supported by the kernel */ > - ipa_max = (pa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : pa_max; > - /* > - * Since our stage2 table is dependent on the stage1 page table code, > - * we must always honor the following condition: > - * > - * Number of levels in Stage1 >= Number of levels in Stage2. > - * > - * So clamp the ipa limit further down to limit the number of levels. > - * Since we can concatenate upto 16 tables at entry level, we could > - * go upto 4bits above the maximum VA addressable with the current > - * number of levels. > - */ > - va_max = PGDIR_SHIFT + PAGE_SHIFT - 3; > - va_max += 4; > - > - if (va_max < ipa_max) > - ipa_max = va_max; > - > - /* > - * If the final limit is lower than the real physical address > - * limit of the CPUs, report the reason. > - */ > - if (ipa_max < pa_max) > - pr_info("kvm: Limiting the IPA size due to kernel %s Address limit\n", > - (va_max < pa_max) ? "Virtual" : "Physical"); > - > - WARN(ipa_max < KVM_PHYS_SHIFT, > - "KVM IPA limit (%d bit) is smaller than default size\n", ipa_max); > - kvm_ipa_limit = ipa_max; > + kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange); > + WARN(kvm_ipa_limit < KVM_PHYS_SHIFT, > + "KVM IPA limit (%d bit) is smaller than default size\n", > + kvm_ipa_limit); > kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit); > > return 0; > Thanks, Gavin _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm