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[31.172.191.173]) by smtp.googlemail.com with ESMTPSA id f12sm22865693pgq.52.2019.07.18.05.13.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Jul 2019 05:13:49 -0700 (PDT) Subject: Re: [PATCH 43/59] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 To: Alexandru Elisei , Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org References: <20190621093843.220980-1-marc.zyngier@arm.com> <20190621093843.220980-44-marc.zyngier@arm.com> <4cd8b175-7676-0d3b-2853-365a346e1302@arm.com> From: Tomasz Nowicki Message-ID: <852db652-5318-113b-083c-baf12eb58593@semihalf.com> Date: Thu, 18 Jul 2019 14:13:45 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Firefox/60.0 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: <4cd8b175-7676-0d3b-2853-365a346e1302@arm.com> Content-Language: en-GB Cc: Andre Przywara , Dave Martin X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hello Alex, On 09.07.2019 15:20, Alexandru Elisei wrote: > On 6/21/19 10:38 AM, Marc Zyngier wrote: >> From: Jintack Lim >> >> When supporting nested virtualization a guest hypervisor executing AT >> instructions must be trapped and emulated by the host hypervisor, >> because untrapped AT instructions operating on S1E1 will use the wrong >> translation regieme (the one used to emulate virtual EL2 in EL1 instead > > I think that should be "regime". > >> of virtual EL1) and AT instructions operating on S12 will not work from >> EL1. >> >> This patch does several things. >> >> 1. List and define all AT system instructions to emulate and document >> the emulation design. >> >> 2. Implement AT instruction handling logic in EL2. This will be used to >> emulate AT instructions executed in the virtual EL2. >> >> AT instruction emulation works by loading the proper processor >> context, which depends on the trapped instruction and the virtual >> HCR_EL2, to the EL1 virtual memory control registers and executing AT >> instructions. Note that ctxt->hw_sys_regs is expected to have the >> proper processor context before calling the handling >> function(__kvm_at_insn) implemented in this patch. >> >> 4. Emulate AT S1E[01] instructions by issuing the same instructions in >> EL2. We set the physical EL1 registers, NV and NV1 bits as described in >> the AT instruction emulation overview. > > Is item number 3 missing, or is that the result of an unfortunate typo? > >> >> 5. Emulate AT A12E[01] instructions in two steps: First, do the stage-1 >> translation by reusing the existing AT emulation functions. Second, do >> the stage-2 translation by walking the guest hypervisor's stage-2 page >> table in software. Record the translation result to PAR_EL1. >> >> 6. Emulate AT S1E2 instructions by issuing the corresponding S1E1 >> instructions in EL2. We set the physical EL1 registers and the HCR_EL2 >> register as described in the AT instruction emulation overview. >> >> 7. Forward system instruction traps to the virtual EL2 if the corresponding >> virtual AT bit is set in the virtual HCR_EL2. >> >> [ Much logic above has been reworked by Marc Zyngier ] >> >> Signed-off-by: Jintack Lim >> Signed-off-by: Marc Zyngier >> Signed-off-by: Christoffer Dall >> --- >> arch/arm64/include/asm/kvm_arm.h | 2 + >> arch/arm64/include/asm/kvm_asm.h | 2 + >> arch/arm64/include/asm/sysreg.h | 17 +++ >> arch/arm64/kvm/hyp/Makefile | 1 + >> arch/arm64/kvm/hyp/at.c | 217 +++++++++++++++++++++++++++++++ >> arch/arm64/kvm/hyp/switch.c | 13 +- >> arch/arm64/kvm/sys_regs.c | 202 +++++++++++++++++++++++++++- >> 7 files changed, 450 insertions(+), 4 deletions(-) >> create mode 100644 arch/arm64/kvm/hyp/at.c >> [...] >> + >> +void __kvm_at_s1e01(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) >> +{ >> + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; >> + struct mmu_config config; >> + struct kvm_s2_mmu *mmu; >> + >> + /* >> + * We can only get here when trapping from vEL2, so we're >> + * translating a guest guest VA. >> + * >> + * FIXME: Obtaining the S2 MMU for a a guest guest is horribly >> + * racy, and we may not find it. >> + */ >> + spin_lock(&vcpu->kvm->mmu_lock); >> + >> + mmu = lookup_s2_mmu(vcpu->kvm, >> + vcpu_read_sys_reg(vcpu, VTTBR_EL2), >> + vcpu_read_sys_reg(vcpu, HCR_EL2)); > From ARM DDI 0487D.b, the description for AT S1E1R (page C5-467, it's the same > for the other at s1e{0,1}* instructions): > > [..] Performs stage 1 address translation, with permisions as if reading from > the given virtual address from EL1, or from EL2 [..], using the following > translation regime: > - If HCR_EL2.{E2H,TGE} is {1, 1}, the EL2&0 translation regime, accessed from EL2. > > If the guest is VHE, I don't think there's any need to switch mmus. The AT > instruction will use the physical EL1&0 translation regime already on the > hardware (assuming host HCR_EL2.TGE == 0), which is the vEL2&0 regime for the > guest hypervisor. Here we want to run AT for L2 (guest guest) EL1&0 regime and not the L1 (guest hypervisor) so we have to lookup and switch to nested VM MMU context. Or did I miss your point? Thanks, Tomasz _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm