From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A4B23E410D for ; Wed, 30 Sep 2026 12:21:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790770915; cv=none; b=ewvsuTIKabe16ZIs3sanIJRb6TWxkegNau1oe8J65TYoeq3hHxrtGT9TDXb42IujdNqK4PepYILhPqHLmfwIOwq8weEVL/DkAwBAoE80SIHrvopPrG+EehoKoOZUSF7qnGXucvteH25oI2BykplYRiC1crMzwahIkb9f1MnttaE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790770915; c=relaxed/simple; bh=esZ9I1R2d4eGNBAf4nkCzm3T23UfWjGyfq/9qby2hPA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=R8i61/AN18t+aArZHy9iHHO4OFYnWsBORXO2ozAgcQZrZxDrJVpoP3BYDKz+IPfBFgOHpBXFQMpakDEbkvtoM+UIyOG8uKOo2RzBDQG3kSeV91FJPr8vnJwF8aLyHtW1VZlZKUgLJ/KoWf+QoKc5snoaYgxD/8Ffd5pm1qR+7Tw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RUL/62yV; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RUL/62yV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1F871F00893; Wed, 30 Sep 2026 12:21:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790770913; bh=wbnq+E++cImxNLsHc1xBt+/AJpyKloWUAjUGIfft+Uw=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=RUL/62yVZtFdGN5Ebnz10BC0cO9q87LtOYTXztxig2qcgS2rV7uKQnP89B731dDPl /iC5MiDm69ELaZlIzZqN/BKEeGAEN+KWsHwOFq02yfczZ2Y+mxa8WbI8oXZprwqz89 rEGt3HndQEAc8mhEVz8DGZFbPAjE0fFbTA9pZ9LVTSTZP/PWFA9nV1pfU+tm3DZxXc 9DK0nFeRyc6FGCxZxqSApSWMeBPtew6ZCDh99zcJiMJlk2I/6rq2wZOPYUnNlaqNUK yJcVCWyTAPm+o5XlcIiElMC75I982yBdqgtpjgwF542o58RY41ksy4miknPoihdFa5 9c9M71Jklsk6g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xBtJn-0000000FJ5O-2v6B; Wed, 30 Sep 2026 12:21:51 +0000 Date: Wed, 30 Sep 2026 13:21:51 +0100 Message-ID: <861pab3p5s.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Steffen Eiden , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Yuchao Zhang , Fuad Tabba Subject: Re: [PATCH v1 2/2] KVM: arm64: selftests: Add an ITS MOVALL test In-Reply-To: References: <20260929093548.3598547-1-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: fuad.tabba@linux.dev, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, seiden@linux.ibm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, ndaugoing@gmail.com, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 29 Sep 2026 20:04:52 +0100, Fuad Tabba wrote: > > Map LPI A to vCPU0's collection and LPI B to vCPU1's, remap vCPU0's > collection to vCPU2 and MOVALL vCPU0's LPIs there, then inject both. A > must be taken on vCPU2 and B on vCPU1. KVM's MAPC handling already moves > A to vCPU2, so only MOVALL handling can move B: without "KVM: arm64: > vgic-its: Fix MOVALL handling of source redistributor", it moves B to > vCPU2 as well. MOVALL is about moving the pending bits (see 5.3.13 in the IHI0069H.b spec). Doing MOVALL first and only then injecting the interrupts doesn't quite check the MOVALL requirement. That doesn't impact KVM itself (we don't use pending tables at all), but you probably don't want to hardcode implementation specific behaviours here. > > Assisted-by: LLM > Signed-off-by: Fuad Tabba > --- > tools/testing/selftests/kvm/Makefile.kvm | 1 + > .../selftests/kvm/arm64/vgic_its_movall.c | 341 ++++++++++++++++++ > 2 files changed, 342 insertions(+) > create mode 100644 tools/testing/selftests/kvm/arm64/vgic_its_movall.c > > diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selftests/kvm/Makefile.kvm > index 908bdc7cf4f58..fb0bc99242975 100644 > --- a/tools/testing/selftests/kvm/Makefile.kvm > +++ b/tools/testing/selftests/kvm/Makefile.kvm > @@ -190,6 +190,7 @@ TEST_GEN_PROGS_arm64 += arm64/stage2_block_transitions > TEST_GEN_PROGS_arm64 += arm64/vcpu_width_config > TEST_GEN_PROGS_arm64 += arm64/vgic_init > TEST_GEN_PROGS_arm64 += arm64/vgic_irq > +TEST_GEN_PROGS_arm64 += arm64/vgic_its_movall > TEST_GEN_PROGS_arm64 += arm64/vgic_its_save > TEST_GEN_PROGS_arm64 += arm64/vgic_lpi_stress > TEST_GEN_PROGS_arm64 += arm64/vgic_v5 > diff --git a/tools/testing/selftests/kvm/arm64/vgic_its_movall.c b/tools/testing/selftests/kvm/arm64/vgic_its_movall.c > new file mode 100644 > index 0000000000000..41918576bdf63 > --- /dev/null > +++ b/tools/testing/selftests/kvm/arm64/vgic_its_movall.c > @@ -0,0 +1,341 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * vgic_its_movall - MOVALL does not move the LPIs of other redistributors. > + * > + * Two LPIs, A and B, target two different redistributors. A's collection is > + * remapped to a third redistributor with MAPC, followed by MOVALL from the > + * first redistributor to the third. Both LPIs are then injected. A must be > + * taken on the third redistributor, and B must stay on its own, which is not > + * MOVALL's source. > + * > + * Copyright (c) 2026 Google LLC > + * Author: Fuad Tabba > + */ > + > +#include > +#include > +#include > + > +#include "kvm_util.h" > +#include "gic.h" > +#include "gic_v3.h" > +#include "gic_v3_its.h" > +#include "processor.h" > +#include "ucall.h" > +#include "vgic.h" > + > +#define TEST_MEMSLOT_INDEX 1 > + > +#define GIC_LPI_OFFSET 8192 > +#define NR_VCPUS 3 > +#define NR_LPIS 2 > +#define DEVICE_ID 0 > + > +/* LPI A (event 0) starts on vCPU0 and moves to vCPU2; B (event 1) stays on vCPU1 */ > +#define LPI_A_COLL 0 > +#define LPI_B_COLL 1 > +#define MOVALL_FROM 0 > +#define MOVALL_TO 2 > +#define LPI_B_VCPU 1 > + > +#define LPI_PROP_DEFAULT_PRIO 0xa0 > + > +static gpa_t gpa_base; > + > +static struct kvm_vm *vm; > +static struct kvm_vcpu *vcpus[NR_VCPUS]; > +static int its_fd; > + > +static struct test_data { > + bool request_vcpus_stop; > + > + gpa_t device_table; > + gpa_t collection_table; > + gpa_t cmdq_base; > + void *cmdq_base_va; > + gpa_t itt_table; > + > + gpa_t lpi_prop_table; > + gpa_t lpi_pend_tables; > +} test_data; There seem to be a lot of commonality with the existing vgic_lpi_stress test. I'd rather we make this test the container for most ITS-related tests, instead of coming up with new individual tests. Thanks, N, -- Without deviation from the norm, progress is not possible.