From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C0F03D47A6; Wed, 9 Sep 2026 07:08:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788937702; cv=none; b=OQGLRh7jAvkVHCzH2IIjv5mC5O4g6f5+i0dBuetQ1IpQcxU6RQkiyMl5tu98/sbx+OdkH7wdMUAl1jF/ZQLTj9sauhQMO9/D+/e+fuhwgOhTlMxVfeXTujBBhxQCDp446ryAyn8tPk7jWbMOjxDQQcw3eEvNnMftyjJrUw2oDqk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788937702; c=relaxed/simple; bh=85m/WVhRK0Nr70jzw6PM0hOCCKtox/kbNoSOiIKqMQw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=KpQFIn2cRbn5Rv8VyK4LYqITB7hi9CJ9lLKwpr53/5Qyug+kPFLCBWcefcAM1CqeuX3o7jaLVifrD5U4hwLeh9j7WC8em+a2VMKdBdjlgLnCFJrLC0/Z9LNmBMe7eZrBB2btZ2bx8CctEJOYJAZFRxVSyEJSJin/ogHLjH3F47I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AuNdNzzc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AuNdNzzc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2408F1F00A3A; Wed, 9 Sep 2026 07:08:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788937701; bh=LSejbcK7K/NRWiPAd3V+hVat+1lWh27LQ2BxueYmNfs=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=AuNdNzzcISTmbTnqRhwF26bE3xybA9X5tQJiA7P35wtNOVZuqQ9G2PteliXeDgkB6 PfdWO5f+ElqW3N60CgPjIB6kCqr4jW4hU9geXnKyVnecFP/k7IgU9KTJDVNihRA6lO qt4B7FoaFW6ebPfszA0GqFQ9f1cj3AZkK6HsA/tjPd/wMZvq5Z9siGzppwWzYmKiIl s13x/ZcJZWdXNIm8RRY/OOYMqUVHUEBFbMVhGBuxQuQJ0/vc3fOxdp1htwbPM5M919 sewYJGb04BAPYGmvZTSDSzqsxCwuTMmMX8bNDQZI+6w/nc4jtUudCYwhnQVTp9weEM bFWUPhtMbR59w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1x4CPr-00000006YSG-0cJY; Wed, 09 Sep 2026 07:08:19 +0000 Date: Wed, 09 Sep 2026 08:08:18 +0100 Message-ID: <8633vi52cd.wl-maz@kernel.org> From: Marc Zyngier To: sashiko-reviews@lists.linux.dev Cc: "Mark Brown" , "Oliver Upton" , kvmarm@lists.linux.dev Subject: Re: [PATCH v2] KVM: arm64: Enable S1PIE for hVHE In-Reply-To: <20260908203145.B735E1F00A3A@smtp.kernel.org> References: <20260908-kvm-arm64-nvhe-pie-v2-1-79e42d28cc08@kernel.org> <20260908203145.B735E1F00A3A@smtp.kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashiko-reviews@lists.linux.dev, broonie@kernel.org, oupton@kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 08 Sep 2026 21:31:45 +0100, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Critical] S1PIE permission indirection registers are incorrectly swapped for hVHE mode, zeroing PIRE0_EL2 and causing an immediate fatal Permission Fault upon MMU enable. > -- > > commit 3004dc878365b596c5ed9c6a57b485c6d2028592 > Author: Mark Brown > Subject: KVM: arm64: Enable S1PIE for hVHE > > This patch enables S1PIE for the hypervisor when running in hVHE mode. It > configures permission indirection to map to non-PIE meanings to minimize > page table manipulation changes. It also explicitly configures TCR2_EL2 > when running in VHE or hVHE modes. > > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > [ ... ] > > > @@ -137,8 +137,20 @@ alternative_if ARM64_HAS_CNP > > alternative_else_nop_endif > > msr ttbr0_el2, x2 > > > > - ldr x0, [x0, #NVHE_INIT_TCR_EL2] > > - msr tcr_el2, x0 > > + ldr x1, [x0, #NVHE_INIT_TCR_EL2] > > + msr tcr_el2, x1 > > + > > +alternative_if ARM64_HAS_S1PIE > > + /* S1PIE is only enabled with TCR2_EL2.PIE if we are running hVHE */ > > + mov_q x1, KVM_HVHE_PIR_EL2 > > + msr REG_PIR_EL2, x1 > > + msr REG_PIRE0_EL2, xzr > > [Severity: Critical] > Does this initialization swap the target registers? Since hVHE uses TTBR0_EL2 > for its translation regime, permission indirection for this space is governed > by PIRE0_EL2. By zeroing PIRE0_EL2 and writing the valid permissions to > PIR_EL2, won't this cause the CPU to evaluate execution permissions as No > Access and immediately trigger a Permission Fault when the MMU is enabled? Utter nonsense. Refer to the definition and notice the "unprivileged" qualifier. M. -- Without deviation from the norm, progress is not possible.