From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DE7947B40B for ; Tue, 20 Jan 2026 15:11:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768921907; cv=none; b=p+y95d8kSWAhhvxfQD0cUQo3ciGz492reCvifMP2Csxq9hmAdActE3WQlLkJkjHI6lig6azhqgHP/Lbr8PHcLr16RVF1et8GvJ9ffehec1yXNN0d3uGEVvYkzMCbcBldYFQcoZyYiuW2kDwGmkRSpLbN14hyl1tQ6gHcZ4fCXmY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768921907; c=relaxed/simple; bh=iV6Tlr2fXAywYynuUZ0uzM5sNmgc8XZ/Pw5AAEjOHFY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=GpYKXpDqGATLreTFYGAENr2heEF70sYa/vLJvWdxynO8HlZdSw93UpOu2ARGocGHTg8nJaEOb9vgZEM6pvpjribAZbCF/j9z9obwLgcOQdMFqTY9XevAxbSJqisOPugidQ4Ms15ghEReoK8XIWGyNzpRdNLUmMwEZx+Gm0TFvt0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JgiXGkjU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JgiXGkjU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 357D6C19423; Tue, 20 Jan 2026 15:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768921907; bh=iV6Tlr2fXAywYynuUZ0uzM5sNmgc8XZ/Pw5AAEjOHFY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=JgiXGkjUOR+0FqbbLcANavJz5ADx4fFlwzgmXcm6a0UD8DEe9mptaxfgXRux+wQU9 tKHDq3l1E22BBW6rv8thSmYDjK+f/jPu8koAPwzm+GB7Q4W+BsyhkXFODP3aybjyS2 Ilmajp+yutDJcOf+O8ZZzeROBVAz8Vk/pFC8oiuZXVXZKp7znPh7pb4lus8VtIKUQY KPsE3wZLq8q/C9OQWat3vSb8He3vv9VKfhuaMFto5fnO/VYQzoYxQdF9onYX+1eTzK 2k43jB5wprm7KVeSnqlQEACAhPy8t4g3C2nGWH5jHeEKuDt/HIfsZEQ0McEOzDhpFD RsQ8fKYpX606g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1viDOT-00000003zFF-0BXT; Tue, 20 Jan 2026 15:11:45 +0000 Date: Tue, 20 Jan 2026 15:11:44 +0000 Message-ID: <863440co9b.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org Subject: Re: [PATCH v2 2/5] arm64: Clear HCR_EL2.ATA when MTE is not supported or disabled In-Reply-To: <20251211113828.370370-3-tabba@google.com> References: <20251211113828.370370-1-tabba@google.com> <20251211113828.370370-3-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 11 Dec 2025 11:38:25 +0000, Fuad Tabba wrote: > > If MTE is not supported by the hardware, or is disabled in the kernel > configuration (CONFIG_ARM64_MTE=n) or command line (arm64.nomte), the > kernel stops advertising MTE to userspace and avoids using MTE > instructions. However, this is a software-level disable only. > > When MTE hardware is present and enabled by EL3 firmware, leaving > HCR_EL2.ATA set allows the host to execute MTE instructions (STG, LDG, > etc.) and access allocation tags in physical memory. This creates a > security risk where a malicious or buggy host could lead to system > crashes, undefined behavior, or compromise guests. > > Prevent this by clearing HCR_EL2.ATA when MTE is disabled. Remove it > from the HCR_HOST_NVHE_FLAGS default, and conditionally set it in > cpu_prepare_hyp_mode() only when system_supports_mte() returns true. > This causes MTE instructions to trap to EL2 when HCR_EL2.ATA is cleared. > > Early boot code in head.S temporarily keeps HCR_ATA set to avoid > special-casing initialization paths. This is safe because this code > executes before untrusted code runs and will clear HCR_ATA if MTE is > disabled. > > Signed-off-by: Fuad Tabba > --- > arch/arm64/include/asm/kvm_arm.h | 2 +- > arch/arm64/kernel/head.S | 2 +- > arch/arm64/kvm/arm.c | 4 ++++ > 3 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index 1da290aeedce..a41e3087e00a 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -101,7 +101,7 @@ > HCR_BSU_IS | HCR_FB | HCR_TACR | \ > HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ > HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID1) > -#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) > +#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK) > #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) > #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H | HCR_AMO | HCR_IMO | HCR_FMO) > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index ca04b338cb0d..87a822e5c4ca 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -299,7 +299,7 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) > isb > 0: > > - init_el2_hcr HCR_HOST_NVHE_FLAGS > + init_el2_hcr HCR_HOST_NVHE_FLAGS | HCR_ATA > init_el2_state > > /* Hypervisor stub */ > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index 052bf0d4d0b0..c03006b1c5bc 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -2030,6 +2030,10 @@ static void __init cpu_prepare_hyp_mode(int cpu, u32 hyp_va_bits) > params->hcr_el2 = HCR_HOST_NVHE_PROTECTED_FLAGS; > else > params->hcr_el2 = HCR_HOST_NVHE_FLAGS; > + > + if (system_supports_mte()) > + params->hcr_el2 |= HCR_ATA; > + How about TID5? If you really want to hide MTE, you also need to catch accesses to GMID_EL1. Thanks, M. -- Without deviation from the norm, progress is not possible.