From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH v4 19/21] KVM: arm64: Handle RAS SErrors from EL2 on guest exit Date: Tue, 31 Oct 2017 06:13:21 +0000 Message-ID: <86375z4zge.fsf@arm.com> References: <20171019145807.23251-1-james.morse@arm.com> <20171019145807.23251-20-james.morse@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 7C45A49D4F for ; Tue, 31 Oct 2017 02:11:53 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EVjqRoR14Hcj for ; Tue, 31 Oct 2017 02:11:52 -0400 (EDT) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 05CD049D28 for ; Tue, 31 Oct 2017 02:11:52 -0400 (EDT) In-Reply-To: <20171019145807.23251-20-james.morse@arm.com> (James Morse's message of "Thu, 19 Oct 2017 15:58:05 +0100") List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: James Morse Cc: Jonathan.Zhang@cavium.com, Catalin Marinas , Julien Thierry , Will Deacon , wangxiongfeng2@huawei.com, linux-arm-kernel@lists.infradead.org, Dongjiu Geng , kvmarm@lists.cs.columbia.edu List-Id: kvmarm@lists.cs.columbia.edu On Thu, Oct 19 2017 at 4:58:05 pm BST, James Morse wrote: > We expect to have firmware-first handling of RAS SErrors, with errors > notified via an APEI method. For systems without firmware-first, add > some minimal handling to KVM. > > There are two ways KVM can take an SError due to a guest, either may be a > RAS error: we exit the guest due to an SError routed to EL2 by HCR_EL2.AMO, > or we take an SError from EL2 when we unmask PSTATE.A from __guest_exit. > > The current SError from EL2 code unmasks SError and tries to fence any > pending SError into a single instruction window. It then leaves SError > unmasked. > > With the v8.2 RAS Extensions we may take an SError for a 'corrected' > error, but KVM is only able to handle SError from EL2 if they occur > during this single instruction window... > > The RAS Extensions give us a new instruction to synchronise and > consume SErrors. The RAS Extensions document (ARM DDI0587), > '2.4.1 ESB and Unrecoverable errors' describes ESB as synchronising > SError interrupts generated by 'instructions, translation table walks, > hardware updates to the translation tables, and instruction fetches on > the same PE'. This makes ESB equivalent to KVMs existing > 'dsb, mrs-daifclr, isb' sequence. > > Use the alternatives to synchronise and consume any SError using ESB > instead of unmasking and taking the SError. Set ARM_EXIT_WITH_SERROR_BIT > in the exit_code so that we can restart the vcpu if it turns out this > SError has no impact on the vcpu. > > Signed-off-by: James Morse Reviewed-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny.