From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAD73C3DA7A for ; Mon, 2 Jan 2023 11:46:16 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 122B84B906; Mon, 2 Jan 2023 06:46:16 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@kernel.org Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xDcVLlFSHw2C; Mon, 2 Jan 2023 06:46:12 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 55A044BA5F; Mon, 2 Jan 2023 06:46:12 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E905E4B8B2 for ; Mon, 2 Jan 2023 06:46:11 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OJ9ZZbBk9g03 for ; Mon, 2 Jan 2023 06:46:10 -0500 (EST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 9601E4B877 for ; Mon, 2 Jan 2023 06:46:10 -0500 (EST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2A6C6B80BE6; Mon, 2 Jan 2023 11:46:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D9165C433EF; Mon, 2 Jan 2023 11:46:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672659967; bh=pkoNww/3woHJbKQ2rbbErmlkidtmGFD9xreR1oEQz18=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=TMouMMfYuvBt6CeD3YzniYL1bk940QsJKRtjEG0wIaIzDneHDt4EGseGnORkH+aFs AZsm+RKnLj+uS5sXzuWN4NPH23QvOLWL0qE9MFUmDK0kHQz8ZYuGg0Mq/FNP1bBjdE mgQw/xEjxPKnXYMF3FYY1gjric5pOoNiaQuwfCqqOvq2iX+ZgnJzGwrGsIdFyVdjvK a22YCyzepbbav1zySKw5TsZnwmcgmBVq4JrYG7DVp7c/VP61cPnC6b2lbAEuqd4YvV hqnQW9J3MQg6nF9C9P48/yQiHQhXc/c72C+VxGM5HJtojUITysONe2QcOlURlTqHmw kUm2f7Z0axy2w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pCJGX-00GJRt-HQ; Mon, 02 Jan 2023 11:46:05 +0000 Date: Mon, 02 Jan 2023 11:46:05 +0000 Message-ID: <867cy5b1mq.wl-maz@kernel.org> From: Marc Zyngier To: Ganapatrao Kulkarni Subject: Re: [PATCH 2/3] KVM: arm64: nv: Emulate ISTATUS when emulated timers are fired. In-Reply-To: <87y1qqe2pg.wl-maz@kernel.org> References: <20220824060304.21128-1-gankulkarni@os.amperecomputing.com> <20220824060304.21128-3-gankulkarni@os.amperecomputing.com> <87y1qqe2pg.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: gankulkarni@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, scott@os.amperecomputing.com, keyur@os.amperecomputing.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: scott@os.amperecomputing.com, kvm@vger.kernel.org, catalin.marinas@arm.com, keyur@os.amperecomputing.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, 29 Dec 2022 13:53:15 +0000, Marc Zyngier wrote: > > On Wed, 24 Aug 2022 07:03:03 +0100, > Ganapatrao Kulkarni wrote: > > > > Guest-Hypervisor forwards the timer interrupt to Guest-Guest, if it is > > enabled, unmasked and ISTATUS bit of register CNTV_CTL_EL0 is set for a > > loaded timer. > > > > For NV2 implementation, the Host-Hypervisor is not emulating the ISTATUS > > bit while forwarding the Emulated Vtimer Interrupt to Guest-Hypervisor. > > This results in the drop of interrupt from Guest-Hypervisor, where as > > Host Hypervisor marked it as an active interrupt and expecting Guest-Guest > > to consume and acknowledge. Due to this, some of the Guest-Guest vCPUs > > are stuck in Idle thread and rcu soft lockups are seen. > > > > This issue is not seen with NV1 case since the register CNTV_CTL_EL0 read > > trap handler is emulating the ISTATUS bit. > > > > Adding code to set/emulate the ISTATUS when the emulated timers are fired. > > > > Signed-off-by: Ganapatrao Kulkarni > > --- > > arch/arm64/kvm/arch_timer.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > > index 27a6ec46803a..0b32d943d2d5 100644 > > --- a/arch/arm64/kvm/arch_timer.c > > +++ b/arch/arm64/kvm/arch_timer.c > > @@ -63,6 +63,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, > > struct arch_timer_context *timer, > > enum kvm_arch_timer_regs treg); > > static bool kvm_arch_timer_get_input_level(int vintid); > > +static u64 read_timer_ctl(struct arch_timer_context *timer); > > > > static struct irq_ops arch_timer_irq_ops = { > > .get_input_level = kvm_arch_timer_get_input_level, > > @@ -356,6 +357,8 @@ static enum hrtimer_restart kvm_hrtimer_expire(struct hrtimer *hrt) > > return HRTIMER_RESTART; > > } > > > > + /* Timer emulated, emulate ISTATUS also */ > > + timer_set_ctl(ctx, read_timer_ctl(ctx)); > > Why should we do that for non-NV2 configurations? > > > kvm_timer_update_irq(vcpu, true, ctx); > > return HRTIMER_NORESTART; > > } > > @@ -458,6 +461,8 @@ static void timer_emulate(struct arch_timer_context *ctx) > > trace_kvm_timer_emulate(ctx, should_fire); > > > > if (should_fire != ctx->irq.level) { > > + /* Timer emulated, emulate ISTATUS also */ > > + timer_set_ctl(ctx, read_timer_ctl(ctx)); > > kvm_timer_update_irq(ctx->vcpu, should_fire, ctx); > > return; > > } > > I'm not overly keen on this. Yes, we can set the status bit there. But > conversely, the bit will not get cleared when the guest reprograms the > timer, and will take a full exit/entry cycle for it to appear. > > Ergo, the architecture is buggy as memory (the VNCR page) cannot be > used to emulate something as dynamic as a timer. > > It is only with FEAT_ECV that we can solve this correctly by trapping > the counter/timer accesses and emulate them for the guest hypervisor. > I'd rather we add support for that, as I expect all the FEAT_NV2 > implementations to have it (and hopefully FEAT_FGT as well). So I went ahead and implemented some very basic FEAT_ECV support to correctly emulate the timers (trapping the CTL/CVAL accesses). Performance dropped like a rock (~30% extra overhead) for L2 exit-heavy workloads that are terminated in userspace, such as virtio. For those workloads, vcpu_{load,put}() in L1 now generate extra traps, as we save/restore the timer context, and this is enough to make things visibly slower, even on a pretty fast machine. I managed to get *some* performance back by satisfying CTL/CVAL reads very early on the exit path (a pretty common theme with NV). Which means we end-up needing something like what you have -- only a bit more complete. I came up with the following: diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 4945c5b96f05..a198a6211e2a 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -450,6 +450,25 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, { int ret; + /* + * Paper over NV2 brokenness by publishing the interrupt status + * bit. This still results in a poor quality of emulation (guest + * writes will have no effect until the next exit). + * + * But hey, it's fast, right? + */ + if (vcpu_has_nv2(vcpu) && is_hyp_ctxt(vcpu) && + (timer_ctx == vcpu_vtimer(vcpu) || timer_ctx == vcpu_ptimer(vcpu))) { + u32 ctl = timer_get_ctl(timer_ctx); + + if (new_level) + ctl |= ARCH_TIMER_CTRL_IT_STAT; + else + ctl &= ~ARCH_TIMER_CTRL_IT_STAT; + + timer_set_ctl(timer_ctx, ctl); + } + timer_ctx->irq.level = new_level; trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq, timer_ctx->irq.level); which reports the interrupt state in all cases. Does this work for you? Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm