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Sat, 15 Feb 2020 10:28:41 +0000 Date: Sat, 15 Feb 2020 10:28:39 +0000 Message-ID: <868sl46t60.wl-maz@kernel.org> From: Marc Zyngier To: Robin Murphy Subject: Re: [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure In-Reply-To: References: <20200214183615.25498-1-maz@kernel.org> <20200214183615.25498-2-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Fri, 14 Feb 2020 22:01:01 +0000, Robin Murphy wrote: Hi Robin, > > Hi Marc, > > On 2020-02-14 6:36 pm, Marc Zyngier wrote: > [...] > > @@ -585,6 +585,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > > pmc->idx != ARMV8_PMU_CYCLE_IDX) > > return; > > + /* > > + * If we have a filter in place and that the event isn't allowed, do > > + * not install a perf event either. > > + */ > > + if (vcpu->kvm->arch.pmu_filter && > > + !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) > > + return; > > If I'm reading the derivation of eventsel right, this will end up > treating cycle counter events (aliased to SW_INCR) differently from > CPU_CYCLES, which doesn't seem desirable. Indeed, this doesn't look quite right. Looking at the description of event 0x11, it doesn't seem to count exactly like the cycle counter (there are a number of PMCR controls affecting it). But none of these actually apply to our PMU emulation (no secure mode, and the idea of dealing with virtual EL2 in the context of the PMU is... not appealing). Now, given that we implement the cycle counter with event 0x11 anyway, I don't think there is any reason to deal with them separately. > Also, if the user did try to blacklist SW_INCR for ridiculous > reasons, we'd need to special-case kvm_pmu_software_increment() to > make it (not) work as expected, right? I thought of that one, and couldn't see a reason to blacklist it (after all, the guest could also increment a variable) and send itself an interrupt. I'm tempted to simply document that event 0 is never filtered. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm