From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22A24298CDE for ; Tue, 5 Aug 2025 18:41:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754419289; cv=none; b=q9E1r3Yul7q+XAkIGV48QXGSp1Hu5AtsHoBEHPiqGDGrShGGtTDFqqOY5+aHqSEUzEbDX1uR89n56aYoW9nhScdJn1/iwKLTYRV45FeLo2a3YRwBVk8Kb5sAUuh8+zmi4xBe7PIiNM98p826ibKHBhfsVMgEZ5JH7IYJkS/KZNk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754419289; c=relaxed/simple; bh=uD11fUjResybtgXeRjv89oPYdFDMt5vMpFniG+hDzd8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=H1Q+D7yNMTONxHb+yn8S5DmyEIysh2iey6y2ACmpyBxd2vDTBBa2nl12+KdEuCC5tIcLopxBdxnCffWnVSefGZKxEJ+f/WHxgrvHJ+oc8Sm9z7TuL0FKEAeJZAZIQvVHSKECPTJFOq0SAOxA1nxHklGrtLjxW0RRNa6WxpX0sIM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BZlDorHx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BZlDorHx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8238C4CEF0; Tue, 5 Aug 2025 18:41:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754419289; bh=uD11fUjResybtgXeRjv89oPYdFDMt5vMpFniG+hDzd8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=BZlDorHxq6qUpw+ESL8LNjn4/KQtwOQtiyp2gso4NevuBnyOmX7dF/d8BR4FBTCJ9 +bRV6K4Hi6t1ldnVjfwQrURP50Dppd2O4f8VRFq6rGSXgNOUQJoE1LO1FQf3HMpYvw oC6ozpTr+8oVDTEZDJhOR+QxZGPicxKcJ4cyBRa9ydzgkDgWjqlNzlrbbMcGyP8Lli yNjEd9zS9a+viAFkNuAXjIMs6Bbw9FtyQrDfkl45+GIyIbB9Rk1YT8R152XLaC/dAz Bp5OmEQaoTbbpLZ0viPsv2VS7UPY12r3YQjOqHsQGSdUYr1OY3UOeE+SEwSnIQmkjo I69VD6kwInbfQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1ujMbG-004FWi-QC; Tue, 05 Aug 2025 19:41:26 +0100 Date: Tue, 05 Aug 2025 19:41:26 +0100 Message-ID: <86cy99a9wp.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vdonnefort@google.com, qperret@google.com, sebastianene@google.com, keirf@google.com, smostafa@google.com Subject: Re: [PATCH v1 3/4] KVM: arm64: Sync protected guest VBAR_EL1 on injecting an undef exception In-Reply-To: <20250805135617.831971-4-tabba@google.com> References: <20250805135617.831971-1-tabba@google.com> <20250805135617.831971-4-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vdonnefort@google.com, qperret@google.com, sebastianene@google.com, keirf@google.com, smostafa@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 05 Aug 2025 14:56:16 +0100, Fuad Tabba wrote: > > In pKVM, a race condition can occur if a guest updates its VBAR_EL1 > register and, before a vCPU exit synchronizes this change, the > hypervisor needs to inject an undefined exception into a protected > guest. > > In this scenario, the vCPU still holds the stale VBAR_EL1 value from > before the guest's update. When pKVM injects the exception, it ends up > using the stale value. > > Explicitly read the live value of VBAR_EL1 from the guest and update the > vCPU value immediately before pending the exception. This ensures the > vCPU's value is the same as the guest's and that the exception will be > handled at the correct address upon resuming the guest. > > Signed-off-by: Fuad Tabba > --- > arch/arm64/kvm/hyp/nvhe/sys_regs.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c > index bbd60013cf9e..b34b10be1ad7 100644 > --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c > +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c > @@ -253,6 +253,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu) > > *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR); > *vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR); > + vcpu_write_sys_reg(vcpu, read_sysreg_el1(SYS_VBAR), VBAR_EL1); > > kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC); > There is something I don't understand. vcpu_write_sys_reg() is only useful if you make use of the SYSREGS_ON_CPU flag. Which is only driven by the VHE code (in arch/arm64/kvm/hyp/vhe/sysreg-sr.c). As a consequence, this only writes to memory, since the flag is always false, and we take the following path: static inline void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) { u64 (*xlate)(u64) = NULL; unsigned int el1r; if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) goto memory_write; [...] memory_write: __vcpu_assign_sys_reg(vcpu, reg, val); } My conclusion so far is that you only ever need to write to the shadow view of the register, and that the previous patch serves no purpose. Am I missing anything? M. -- Without deviation from the norm, progress is not possible.