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Thu, 08 Feb 2024 13:15:28 +0000 Date: Thu, 08 Feb 2024 13:15:27 +0000 Message-ID: <86il2z5c7k.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , Catalin Marinas , Will Deacon , Mark Rutland , Suzuki K Poulose , Ard Biesheuvel , James Morse , Oliver Upton , Zenghui Yu Subject: Re: [PATCH v4 04/10] arm64: sysreg: Add layout for ID_AA64MMFR4_EL1 In-Reply-To: References: <20240122181344.258974-1-maz@kernel.org> <20240122181344.258974-5-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, suzuki.poulose@arm.com, ardb@kernel.org, james.morse@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 08 Feb 2024 13:06:52 +0000, Miguel Luis wrote: >=20 > Hi Marc, >=20 > > On 22 Jan 2024, at 17:13, Marc Zyngier wrote: > >=20 > > ARMv9.5 has infroduced ID_AA64MMFR4_EL1 with a bunch of new features. > > Add the corresponding layout. > >=20 > > This is extracted from the public ARM SysReg_xml_A_profile-2023-09 > > delivery, timestamped d55f5af8e09052abe92a02adf820deea2eaed717. > >=20 > > Reviewed-by: Suzuki K Poulose > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ > > 1 file changed, 37 insertions(+) > >=20 > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > > index 4c9b67934367..fa3fe0856880 100644 > > --- a/arch/arm64/tools/sysreg > > +++ b/arch/arm64/tools/sysreg > > @@ -1791,6 +1791,43 @@ UnsignedEnum 3:0 TCRX > > EndEnum > > EndSysreg > >=20 > > +Sysreg ID_AA64MMFR4_EL1 3 0 0 7 4 > > +Res0 63:40 > > +UnsignedEnum 39:36 E3DSE > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +Res0 35:28 > > +SignedEnum 27:24 E2H0 > > + 0b0000 IMP > > + 0b1110 NI_NV1 > > + 0b1111 NI > > +EndEnum > > +UnsignedEnum 23:20 NV_frac > > + 0b0000 NV_NV2 > > + 0b0001 NV2_ONLY > > +EndEnum > > +UnsignedEnum 19:16 FGWTE3 > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +UnsignedEnum 15:12 HACDBS > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +UnsignedEnum 11:8 ASID2 > > + 0b0000 NI > > + 0b0001 IMP > > +EndEnum > > +SignedEnum 7:4 EIESB > > + 0b0000 NI > > + 0b0001 ToEL3 > > + 0b0010 ToELx > > + 0b1111 ANY > > +EndEnum > > +Res0 3:0 > > +EndSysreg > > + >=20 > Reviewed-by: Miguel Luis >=20 > Would you please help me understand how the kernel would cope with E2H0= =E2=80=99s > 0b0000 value on systems prior to ARMv9.5 where a read to > ID_AA64MMFR4_EL1 would be RES0 ? E2H0=3D=3D0 means that E2H can be set to 0. Which is what MMFR4 always indicated before the introduction of this anti-feature. On any system where E2H0 reports 0, there is no change at all for SW. Only if you want to correctly deal with a system where E2H0 reports something other than 0 would you need to do something different. Which is what this series is about, mostly. ARMv9.5 doesn't come into play, as this is an allowed anti-feature from ARMv8.1. M. --=20 Without deviation from the norm, progress is not possible.