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From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oliver.upton@linux.dev>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Jinqian Yang <yangjinqian1@huawei.com>
Subject: Re: [PATCH 1/8] KVM: arm64: Enforce absence of FEAT_FGT on FGT registers
Date: Thu, 18 Sep 2025 10:53:06 +0100	[thread overview]
Message-ID: <86jz1w13zx.wl-maz@kernel.org> (raw)
In-Reply-To: <aMuhni_SDxQaAtiU@linux.dev>

On Thu, 18 Sep 2025 07:07:26 +0100,
Oliver Upton <oliver.upton@linux.dev> wrote:
> 
> Hey,
> 
> On Wed, Sep 17, 2025 at 05:58:33PM +0100, Marc Zyngier wrote:
> 
> Did you mean to add changelogs to these patches?

I actually meant to send a *different* series. Pushed out the wrong
branch and sent crap. Apologies for the noise.

> 
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> >  arch/arm64/kvm/config.c | 201 +++++++++++++++++++++++++++-------------
> >  1 file changed, 137 insertions(+), 64 deletions(-)
> > 
> > diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c
> > index da66c4a147752..42b834c82a20d 100644
> > --- a/arch/arm64/kvm/config.c
> > +++ b/arch/arm64/kvm/config.c
> > @@ -8,11 +8,16 @@
> >  #include <asm/sysreg.h>
> >  
> >  struct reg_bits_to_feat_map {
> > -	u64		bits;
> > +	union {
> > +		u64	bits;
> > +		u64	*res0p;
> > +	};
> >  
> >  #define	NEVER_FGU	BIT(0)	/* Can trap, but never UNDEF */
> >  #define	CALL_FUNC	BIT(1)	/* Needs to evaluate tons of crap */
> >  #define	FIXED_VALUE	BIT(2)	/* RAZ/WI or RAO/WI in KVM */
> > +#define	RES0_POINTER	BIT(3)	/* Pointer to RES0 value instead of bits */
> > +
> >  	unsigned long	flags;
> >  
> >  	union {
> > @@ -28,9 +33,16 @@ struct reg_bits_to_feat_map {
> >  	};
> >  };
> >  
> > -#define __NEEDS_FEAT_3(m, f, id, fld, lim)		\
> > +struct reg_to_feat_map {
> > +	const char				*name;
> > +	const struct reg_bits_to_feat_map	feat_map;
> 
> Some documentation might help with confusion between this and
> bit_feat_map. IIUC you're using a single NEEDS_FEAT() expression to RES0
> the whole sucker based on whether or not the FEAT_XXX for the EL2
> register is present?
> 
> > +	const struct reg_bits_to_feat_map	*bit_feat_map;
> > +	const unsigned int			bit_feat_map_sz;
> > +};
> 
> Ok, differentiating "reg_to_feat_map" and "reg_bits_to_feat_map" is a
> bit hard on the reader... Could this maybe be called "reg_feat_map_desc"
> or similar?

Sure thing. Things will be a bit noisier, but hey...

> This refactoring could also be done as a separate patch.

Yup, that's what I already have in the series I was suppose to send...

I'll respin this shortly.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2025-09-18  9:53 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-17 16:58 [PATCH 0/8] KVM: arm64: Handle effective RES0 behaviour of undefined registers Marc Zyngier
2025-09-17 16:58 ` [PATCH 1/8] KVM: arm64: Enforce absence of FEAT_FGT on FGT registers Marc Zyngier
2025-09-18  6:07   ` Oliver Upton
2025-09-18  9:53     ` Marc Zyngier [this message]
2025-09-17 16:58 ` [PATCH 2/8] KVM: arm64: Enforce absence of FEAT_FGT2 on FGT2 registers Marc Zyngier
2025-09-17 16:58 ` [PATCH 3/8] KVM: arm64: Enforce absence of FEAT_HCX on HCRX_EL2 Marc Zyngier
2025-09-17 16:58 ` [PATCH 4/8] KVM: arm64: Convert HCR_EL2 RES0 handling to compute_reg_res0_bits() Marc Zyngier
2025-09-17 16:58 ` [PATCH 5/8] KVM: arm64: Enforce absence of FEAT_SCTLR2 on SCTLR2_EL{1,2} Marc Zyngier
2025-09-17 16:58 ` [PATCH 6/8] KVM: arm64: Enforce absence of FEAT_TCR2 on TCR2_EL2 Marc Zyngier
2025-09-17 16:58 ` [PATCH 7/8] KVM: arm64: Convert SCTLR_EL1 RES0 handling to compute_reg_res0_bits() Marc Zyngier
2025-09-17 16:58 ` [PATCH 8/8] KVM: arm64: Convert MDCR_EL2 " Marc Zyngier

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