Re: [PATCH v5 00/41] arm_mpam: Add KVM/arm64 and resctrl glue code

Ben Horgan
2026-03-04T09:42:31Z

Hi Punit,

On 3/3/26 20:18, Punit Agrawal wrote:
> Hi Ben,
>
> Ben Horgan <ben.horgan@arm.com> writes:
>
>> The main change in this version of the mpam missing pieces series is to
>> update the cdp emulation to match the resctrl interface. L2 and L3
>> resources can now enable cdp separately. Cdp can't be hidden correctly for
>> memory bandwidth allocation, as max per partid can't be emulated with more
>> partids, and so we hide this completely when cdp is enabled. There is a little
>> restructuring and a few smaller changes.
>>
>> Changelogs in patches
>>
>> It would be great to get this series merged this cycle. For that we'll need
>> more testing and reviewing. Thanks!
>>
>> From James' cover letter:
>>
>> This is the missing piece to make MPAM usable resctrl in user-space. This has
>> shed its debugfs code and the read/write 'event configuration' for the monitors
>> to make the series smaller.
>>
>> This adds the arch code and KVM support first. I anticipate the whole thing
>> going via arm64, but if goes via tip instead, the an immutable branch with those
>> patches should be easy to do.
>>
>> Generally the resctrl glue code works by picking what MPAM features it can expose
>> from the MPAM drive, then configuring the structs that back the resctrl helpers.
>> If your platform is sufficiently Xeon shaped, you should be able to get L2/L3 CPOR
>> bitmaps exposed via resctrl. CSU counters work if they are on/after the L3. MBWU
>> counters are considerably more hairy, and depend on hueristics around the topology,
>> and a bunch of stuff trying to emulate ABMC.
>> If it didn't pick what you wanted it to, please share the debug messages produced
>> when enabling dynamic debug and booting with:
>> | dyndbg="file mpam_resctrl.c +pl"
>>
>> I've not found a platform that can test all the behaviours around the monitors,
>> so this is where I'd expect the most bugs.
>>
>> The MPAM spec that describes all the system and MMIO registers can be found here:
>> https://developer.arm.com/documentation/ddi0598/db/?lang=en
>> (Ignored the 'RETIRED' warning - that is just arm moving the documentation around.
>> This document has the best overview)
>>
>>
>> Based on v7.0-rc1
>>
>> The series can be retrieved from:
>> https://gitlab.arm.com/linux-arm/linux-bh.git mpam_resctrl_glue_v5
>
> I booted with the series applied on an MPAM capable platform. The driver
> is able to probe the L2 attached MSCs.
>
> In terms of features, bit-mapped based cache portion partitioning works
> as expected. The platform also supports additional controls (cache
> capacity and priority partitioning) and monitors (memory bandwidth and
> cache storage). The ones supported in MPAM driver probe OK but don't
> seem to be exposed. E.g.,
>
> mpam:mpam_resctrl_pick_counters: class 2 is a cache but not the L3
>
>
> It looks like some of it is due to an impedance mismatch with resctrl

Yes, what you describe is expected behaviour. There is no support yet
for cache capacity (CMAX) or bandwidth priority partitioning and
monitors are only exposed on the L3.

> expectations but hopefully we can get to it with the basics in-place.

I hope so. The CMAX and the bandwidth priority partitioning should be
easy to add once there is a generic way of adding new schema. There is a
plan/discussion here [1] and I don't expect adding monitoring on L2 to
be hard.

[1] https://lore.kernel.org/lkml/aPtfMFfLV1l%2FRB0L@e133380.arm.com/

>
> Feel free to add
>
> Tested-by: Punit Agrawal <punit.agrawal@oss.qualcomm.com>

Thanks for testing!

>
> Thanks,
> Punit
>

Thanks,

Ben