From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B987DF58 for ; Wed, 2 Aug 2023 17:52:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D8EC9C433C8; Wed, 2 Aug 2023 17:52:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690998778; bh=uRYtG8q0OMNIrkxz12A1TeaVWvX+CXQ+DHeCh+Zma2Y=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=gZCs6EzXdrjn6ib1NtkAeFaf71VC84zl6lF1iqVCC2QxjXPpjJVqXjRsRkKrVz7UI G1ch6I/jZ14rH5vM/zYo9at60YPjUv3F9P0LXmXjR83gRLjUAwUuX0ayltPxImQeqz gdjz7dv234YslN5myKZtyELjWtX7f6ZJQoAl0tmd9qlOMmOunc4ahb4hGRb7W+I352 S6GNIH3UwM/fBBZd4lOQOLKLyko1aA0vYFbJ+YYoslhdeZ0yekE8QwRqBebbF1+H70 QEUruCGMptHaFYyhjAZc5yOybW7toswJvhFhRZDM8XGtHxq5gCPZvDTLmQu4BkjQoF +FgpQBaVCUDmg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qRG1o-001Rzi-Ad; Wed, 02 Aug 2023 18:52:56 +0100 Date: Wed, 02 Aug 2023 18:52:55 +0100 Message-ID: <86leet5o20.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Catalin Marinas , Eric Auger , Mark Brown , Mark Rutland , Will Deacon , Alexandru Elisei , Andre Przywara , Chase Conklin , Ganapatrao Kulkarni , Darren Hart , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH v2 06/26] arm64: Add debug registers affected by HDFGxTR_EL2 In-Reply-To: <61B845D3-A42B-451F-B74D-51B4A1FD28C6@oracle.com> References: <20230728082952.959212-1-maz@kernel.org> <20230728082952.959212-7-maz@kernel.org> <61B845D3-A42B-451F-B74D-51B4A1FD28C6@oracle.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, eric.auger@redhat.com, broonie@kernel.org, mark.rutland@arm.com, will@kernel.org, alexandru.elisei@arm.com, andre.przywara@arm.com, chase.conklin@arm.com, gankulkarni@os.amperecomputing.com, darren@os.amperecomputing.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 31 Jul 2023 17:41:41 +0100, Miguel Luis wrote: >=20 > Hi Marc, >=20 > A few comments on this one, please see below. >=20 > > On 28 Jul 2023, at 08:29, Marc Zyngier wrote: > >=20 > > The HDFGxTR_EL2 registers trap a (huge) set of debug and trace > > related registers. Add their encodings (and only that, because > > we really don't care about what these registers actually do at > > this stage). > >=20 > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++ > > 1 file changed, 78 insertions(+) > >=20 > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/s= ysreg.h > > index 76289339b43b..9dfd127be55a 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -194,6 +194,84 @@ > > #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) > > #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) > >=20 > > +#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) = | 0)) > > +#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0) > > +#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) = | 1)) > > +#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1) > > +#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) = | 2)) > > +#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2) > > +#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2) > > + > > +#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0) > > +#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1) > > +#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0) > > + > > +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) > > +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) >=20 > SYS_TRCITECR_EL1 shows up twice. Ah, nice one. Too many registers. >=20 > > +#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)= )) >=20 > Besides m=E2=80=99s restrictions it could be sanitised in op2 to consider= only bit m[3]. > Suggestion for op2: (2 | ((m & 8) >> 3))) It is fully expected that 'm' will be in the 0-15 range, as per the architecture (D19.4.8), and the tables only use that exact range. Do you see an actual bug, or is this defensive programming? Thanks, M. --=20 Without deviation from the norm, progress is not possible.