From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 851AA1D5CF8 for ; Thu, 17 Apr 2025 16:59:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744909188; cv=none; b=tVR3eFBV/zONICrNHCohE8sY7qSfpCLYim+sjy9VkerUGRscF/lig96VIkKbvClngNSe3cgzu9y0kO5lQ3VadQbEdw+mOgPvBaJLq64mQbvUxiyF76YoImzrnQoCPgd9W8uo8P4wOoDDqfcfXxFeCYrXyP1DXAlI/Sju6Qtf0DE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744909188; c=relaxed/simple; bh=4EslEBhr8QIjv8pIHyC/BwXiEvdXtt7Vn/sFJ18+xbk=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=dmNQndBk547YM2ONg9tmnw1vJ2OQXsbXXNhit56zTtmghA3FqL4lg3oJS6w8cc2CzImnpAmVr1PJEYzRLn7qeGCEqWgEsHyUveL2+GzxcPUyg2rQnc1oxgPJCkwPmToxWNkvAKObWKV8f24e5mdf2Kaz3gGLGpOFU16UBIe9ZDk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WaOciruI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WaOciruI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EEF3CC4CEE4; Thu, 17 Apr 2025 16:59:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744909188; bh=4EslEBhr8QIjv8pIHyC/BwXiEvdXtt7Vn/sFJ18+xbk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=WaOciruIaaAOchpsY3VvZlsMrdxiEaI2RjCdIN2u/YjVu0WuN97jPjhpT6EhCtVZS CjW3eXn9ir+nw4qdcg9kM1pTfXZnqgojkylO9dusVt5pCUNLXZiXby+GJsBxbI3KIV MMmBJ/auzN/WX+5Vryhp9hMjlbMtAuyHof8VGyX5TzIzQ3NxrQgwWA2EMpPSyIJTOW iqAQjtv8EaE0WRQwpCLZP8k0lJAqlHjjmj0oj2blQEzlAwl6Arsm1ur3YY3dMzGiEH ZUbGgph/c0dZ20OYJYqM82UeLbufRLQx4kvtCeaj9Dud+EiU6n/DPlpmelRz6NzSic xINrDyYSZhfvA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1u5SaX-006UXz-P9; Thu, 17 Apr 2025 17:59:45 +0100 Date: Thu, 17 Apr 2025 17:59:45 +0100 Message-ID: <86o6wuk9ku.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Ada Couprie Diaz , Catalin Marinas , Shameer Kolothum , Oliver Upton Subject: Re: [PATCH] arm64: Remove checks for broken Cavium HW from the PI code In-Reply-To: <20250417140147.GA13109@willie-the-truck> References: <20250416123534.1108220-1-maz@kernel.org> <20250417140147.GA13109@willie-the-truck> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, ada.coupriediaz@arm.com, catalin.marinas@arm.com, shameerali.kolothum.thodi@huawei.com, oliver.upton@linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 17 Apr 2025 15:01:48 +0100, Will Deacon wrote: > > Hmm, I'm not really sure about this as it seems to be punishing the poor > user of the box who really hasn't done anything wrong. The firmware might > not be passing a KASLR seed to the host, but what about guest VMs? It's > pretty easy for the VMM to stuff a seed into the DT, so if somebody was > running VMs on TX1 with kaslr before c8c2647e69bed ("arm64: Make > _midr_in_range_list() an exported function") and things worked, I don't > think we should be breaking that so that it crashes in weird ways. That's a good point, and I should have thought of that. > Could we just read MIDR_EL1 (read_cpuid_id()) in the PI code to detect > ThunderX that way? I'm less fussed about the multi-MIDR code working on > this machine as it's a new feature (and we could disable the new > hypercalls here if we really cared). Yeah, probably. Let me have a play with this thing again. > Alternatively, we could properly rip out the TX1 support and fail to boot > if we detect it. At least that's deterministic and we could have a useful > error message about the thing being unsupported. That'd be the last resort, and I'd rather keep this machine alive as this is the only v8.0 box I have with 16kB page support. Thanks, M. -- Without deviation from the norm, progress is not possible.