From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F04E1844 for ; Fri, 20 Jan 2023 11:49:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0BA0BC433EF; Fri, 20 Jan 2023 11:49:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674215360; bh=nBv3Z0zN6FIK72fB6cklCmKK6PIxgedt0S7yzYNK6hw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=NGspnuDnCeckCB1H3fnRfpWPtmz4HXhUbeqcuB+GIOpy9BtvBDQOR/ZoVg3Xw10OG 6YMTaYG50bXTlaMK+/2YODwXhYhe2F5LpIw5kpzrxRsYCUpVNTdYSFDaRGeewphNzC Ype4UgPlFo6IsqwxH4OT2RuvCtc01gN6kgx9siexHJ9MCfbbTrDLZz7JGnjkba34XQ bGU6WzXNWJKomCQTeDWnXDeN5tMg0soO69IYbYuzC6PukdFGg/R9LQ613tUq0/Af+w zE6Rm6nQq54mZ4A/tzX6AI6EZDSH6cVFMiF+JBR1Q6BfBxDSM3D7C8/Qs9MfsxxJ69 XDyJgGSJzpl8w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pIptV-003Ofx-IA; Fri, 20 Jan 2023 11:49:17 +0000 Date: Fri, 20 Jan 2023 11:49:17 +0000 Message-ID: <86sfg5mnnm.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon , Suzuki K Poulose Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Catalin Marinas , Mark Rutland , James Morse , Oliver Upton , Zenghui Yu Subject: Re: [PATCH 1/2] KVM: arm64: Disable KVM on systems with a VPIPT i-cache In-Reply-To: <20230120101415.GA21784@willie-the-truck> References: <20230113172523.2063867-1-maz@kernel.org> <20230113172523.2063867-2-maz@kernel.org> <20230120101415.GA21784@willie-the-truck> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, suzuki.poulose@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 20 Jan 2023 10:14:16 +0000, Will Deacon wrote: > > On Fri, Jan 13, 2023 at 05:25:22PM +0000, Marc Zyngier wrote: > > Systems with a VMID-tagged PIPT i-cache have been supported for > > a while by Linux and KVM. However, these systems never appeared > > on our side of the multiverse. > > > > Refuse to initialise KVM on such a machine, should then ever appear. > > Following changes will drop the support from the hypervisor. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/arm.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > index 9c5573bc4614..508deed213a2 100644 > > --- a/arch/arm64/kvm/arm.c > > +++ b/arch/arm64/kvm/arm.c > > @@ -2195,6 +2195,11 @@ int kvm_arch_init(void *opaque) > > int err; > > bool in_hyp_mode; > > > > + if (icache_is_vpipt()) { > > + kvm_info("Incompatible VPIPT I-Cache policy\n"); > > + return -ENODEV; > > + } > > Hmm, does this work properly with late CPU onlining? For example, if my set > of boot CPUs are all friendly PIPT and KVM initialises happily, but then I > late online a CPU with a horrible VPIPT policy, I worry that we'll quietly > do the wrong thing wrt maintenance. Yup. The problem is what do we do in that case? Apart from preventing the late onlining itself? > > If that's the case, then arguably we already have a bug in the cases where > we trap and emulate accesses to CTR_EL0 from userspace because I _think_ > we'll change the L1Ip field at runtime after userspace could've already read > it. > > Is there something that stops us from ended up in this situation? Probably not. Userspace will observe the wrong thing, and this applies to *any* late onlining with a more restrictive cache topology (such as PIPT -> VIPT). Unclear how the trapping will be engaged on the *other* CPUs as well... I've tried to reverse-engineer the cpufeature arrays again, and failed to find a good solution for this. Suzuki, what do you think? M. -- Without deviation from the norm, progress is not possible.