From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91C38261B91 for ; Thu, 22 Jan 2026 11:06:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769080000; cv=none; b=P8gtUvZ19PIXKqscG9qsMWpoOXRtMFWAfwxeSTh9gysG89O7o6IYA2AfMquvmXzqpqXo+RLhAgUKIbHb5Rdj9OLa8IbPp0uaYaBZIzijaFl7lBXSqUPpEKLONDHfHvujMWLdG/kEbEusx2GvGKsSkGBzelP+xR1jsZvCdl+2Grc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769080000; c=relaxed/simple; bh=Mo+fFuWnIyY+jgV07bD38jQAwustmT9SpjnI6YUi2b8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=erWj0rl3xBRa6P2X9kF0OFa5pIj7cM1FmL1jA44xOqMj3J9XWT7eOFCDTKXx5hU4pcOkSv47v41SC76jUwPQkgWwktZBjDvua/PwdCPag4iBk/qtt20tgWxTT6ZDM1LHAXJRKS0ToDNpDidXd/tVAty/TgOz9L575qj2M4/6Jsg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p1b846Gb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p1b846Gb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F093EC116C6; Thu, 22 Jan 2026 11:06:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769080000; bh=Mo+fFuWnIyY+jgV07bD38jQAwustmT9SpjnI6YUi2b8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=p1b846Gb+8Y5s21R+XIbTNsWZpkXO2Ni51bV1WLh2eC+4h27z4S4Wtb/scgL5k/Wf K4dopOW/ez2E1yvXP9Ujc3DruRIGZ25eL8d8MpPQniY8PiBg0qOAEuuap4vBBh8cVG I9i9oFksgbzFK8qQ/dFwIueXQKlVlzPfQAYDK8O+Rfviwj8oqVhVB/gKCtjh3H8S2K yPeclA5ezp/wwvKUE1FWkFvt2cw4dHYjZTYImSc2UIuuUyxHkdDPtQEXqSgI6hCc5a YIgXS89oBkpDZwzroEH4+rKeKrN9Y34d7Ie7iEEmPQuJRqaC9SqMxD3PF31BKOY+gw yq+sIZc3wzS2Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1visWL-00000004emC-2omE; Thu, 22 Jan 2026 11:06:37 +0000 Date: Thu, 22 Jan 2026 11:06:37 +0000 Message-ID: <86tswdc3eq.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Catalin Marinas , Mark Rutland , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH 3/3] arm64: Unconditionally enable EPAN support In-Reply-To: References: <20260107180701.2858276-1-maz@kernel.org> <20260107180701.2858276-4-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, catalin.marinas@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 22 Jan 2026 10:15:56 +0000, Will Deacon wrote: > > On Wed, Jan 07, 2026 at 06:07:01PM +0000, Marc Zyngier wrote: > > While FEAT_PAN3 is pretty recent, having it permanently enabled costs > > exactly nothing, and does help with exec-only mappings on these fancy > > ARMv9.2 machines that are rumoured to exist. > > I'm not sure it's _entirely_ accurate to say this one costs us "exactly > nothing": > > > diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h > > index 177c691914f87..13c0fa54ea19f 100644 > > --- a/arch/arm64/include/asm/cpucaps.h > > +++ b/arch/arm64/include/asm/cpucaps.h > > @@ -19,8 +19,6 @@ cpucap_is_possible(const unsigned int cap) > > "cap must be < ARM64_NCAPS"); > > > > switch (cap) { > > - case ARM64_HAS_EPAN: > > - return IS_ENABLED(CONFIG_ARM64_EPAN); > > case ARM64_SVE: > > return IS_ENABLED(CONFIG_ARM64_SVE); > > case ARM64_SME: > > as this means cpus_have_cap(EPAN) always ends up doing a test_bit(). It's > not exactly expensive, but it feels a little premature when compared to > PAN and LSE so I'll probably just take those changes for now. Ah, fair enough. It can probably wait another few years then! Cheers, M. -- Without deviation from the norm, progress is not possible.