From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 017B319447 for ; Mon, 18 Dec 2023 11:12:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jz+SzucO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7649CC433C7; Mon, 18 Dec 2023 11:12:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702897966; bh=b3qgeC/uwYa0bAnJnS8yTjTGc8YGVC+z+HwE1Gsl07s=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=jz+SzucOjnNFhYTnbfhox/DuNTjCitlCXduJrd8TCV3KrvwrmPa2NorJ3QS1Uztwj uTxsqKn2z1YmGBhvrbghxgMGhezEH5+JVgfD27ZvWam5nOz41FF38cNuU3WzwPVWzu pWfaroKLOGY6Ko6dDsuY6zMobwG72ff/uOH2zrr2LHT2OiwvEo+Ij8H+z1DHSPyP55 nscFyaMGwDLGVHaziqcwfnd6/20WHVZMt9iuaDMB1XtWtExc6fPHQtPtJ91Dkjc9yG 9AY7qOh9Zgdoe3qSeMNB7IY5VCcPW+HRdXvrpuLM9dnVc/YokgMNI8T7YXDXBMyp/0 jhKsuLwBml1UQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rFBYB-0050pv-UT; Mon, 18 Dec 2023 11:12:44 +0000 Date: Mon, 18 Dec 2023 11:12:43 +0000 Message-ID: <86v88vahn8.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, oliver.upton@linux.dev, broonie@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, eric.auger@redhat.com, jingzhangos@google.com, joey.gouly@arm.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits In-Reply-To: References: <20231214100158.2305400-1-tabba@google.com> <20231214100158.2305400-15-tabba@google.com> <86wmtbalx9.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, oliver.upton@linux.dev, broonie@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, eric.auger@redhat.com, jingzhangos@google.com, joey.gouly@arm.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 18 Dec 2023 09:56:32 +0000, Fuad Tabba wrote: >=20 > Hi Marc, >=20 > On Mon, Dec 18, 2023 at 9:40=E2=80=AFAM Marc Zyngier wro= te: > > > > On Thu, 14 Dec 2023 10:01:54 +0000, > > Fuad Tabba wrote: > > > > > > There's a lot of boilerplate code for setting and clearing FGT > > > bits when activating guest traps. Refactor it into macros. These > > > macros will also be used in future patch series. > > > > > > No functional change intended. > > > > > > Signed-off-by: Fuad Tabba > > > --- > > > arch/arm64/kvm/hyp/include/hyp/switch.h | 60 +++++++++--------------= -- > > > 1 file changed, 21 insertions(+), 39 deletions(-) > > > > > > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm= /hyp/include/hyp/switch.h > > > index 17ce40f5b006..e223fc0d5193 100644 > > > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h > > > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h > > > @@ -79,6 +79,23 @@ static inline void __activate_traps_fpsimd32(struc= t kvm_vcpu *vcpu) > > > clr |=3D ~hfg & __ ## reg ## _nMASK; = \ > > > } while(0) > > > > > > +#define update_fgt_traps_cs(reg, clr, set) = \ > > > + do { = \ > > > + struct kvm_cpu_context *hctxt =3D = \ > > > + &this_cpu_ptr(&kvm_host_data)->host_ctxt; = \ > > > + u64 val, c =3D 0, s =3D 0; = \ > > > + = \ > > > + ctxt_sys_reg(hctxt, reg) =3D read_sysreg_s(SYS_ ## reg)= ; \ > > > + compute_clr_set(vcpu, reg, c, s); = \ > > > > You are referring to a variable name that is in the scope of the macro > > user, and not the macro itself. It is so fragile it isn't funny. > > > > Why don't you simply pass the vcpu as a parameter to the function? > > > > Another thing is that this read/write can be expensive. How about not > > doing anything when there is no change to the value of the sysreg? >=20 > What do you think of this (spacing will be fixed): >=20 > #define update_fgt_traps_cs(vcpu, reg, clr, set) \ > do { > \ > struct kvm_cpu_context *hctxt =3D > \ > &this_cpu_ptr(&kvm_host_data)->host_ctxt; \ > u64 val, c =3D 0, s =3D 0; > \ >=20 > \ > ctxt_sys_reg(hctxt, reg) =3D read_sysreg_s(SYS_ ## reg); \ > compute_clr_set(vcpu, reg, c, s); > \ > val =3D __ ## reg ## _nMASK; > \ > val |=3D (s | set); > \ > val &=3D ~(c | clr); > \ > if (ctxt_sys_reg(hctxt, reg) !=3D val) > \ > write_sysreg_s(val, SYS_ ## reg); > \ > } while(0) >=20 > If it looks good to you, I'll fix it on the respin. This is what I have on top at the moment: diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 27077e1f7de2..d56fef44dc31 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -79,22 +79,26 @@ static inline void __activate_traps_fpsimd32(struct kvm= _vcpu *vcpu) clr |=3D ~hfg & __ ## reg ## _nMASK; \ } while(0) =20 -#define update_fgt_traps_cs(reg, clr, set) \ +#define update_fgt_traps_cs(vcpu, reg, clr, set) \ do { \ struct kvm_cpu_context *hctxt =3D \ &this_cpu_ptr(&kvm_host_data)->host_ctxt; \ - u64 val, c =3D 0, s =3D 0; \ + u64 c =3D 0, s =3D 0; \ \ ctxt_sys_reg(hctxt, reg) =3D read_sysreg_s(SYS_ ## reg); \ compute_clr_set(vcpu, reg, c, s); \ - val =3D __ ## reg ## _nMASK; \ - val |=3D (s | set); \ - val &=3D ~(c | clr); \ - write_sysreg_s(val, SYS_ ## reg); \ + s |=3D set; \ + c |=3D clr; \ + if (c || s) { \ + u64 val =3D __ ## reg ## _nMASK; \ + val |=3D s; \ + val &=3D ~c; \ + write_sysreg_s(val, SYS_ ## reg); \ + } \ } while(0) =20 -#define update_fgt_traps(reg) \ - update_fgt_traps_cs(reg, 0, 0) +#define update_fgt_traps(vcpu, reg) \ + update_fgt_traps_cs(vcpu, reg, 0, 0) =20 /* * Validate the fine grain trap masks. @@ -171,9 +175,9 @@ static inline void __activate_traps_hfgxtr(struct kvm_v= cpu *vcpu) if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu)) return; =20 - update_fgt_traps(HFGITR_EL2); - update_fgt_traps(HDFGRTR_EL2); - update_fgt_traps(HDFGWTR_EL2); + update_fgt_traps(vcpu, HFGITR_EL2); + update_fgt_traps(vcpu, HDFGRTR_EL2); + update_fgt_traps(vcpu, HDFGWTR_EL2); =20 if (cpu_has_amu()) update_fgt_traps(vcpu, HAFGRTR_EL2); If that seems sensible to you, I'll fold it in, as I'd like to do without a respin if we can avoid it. ` M. --=20 Without deviation from the norm, progress is not possible.