From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D66742A82; Thu, 12 Jun 2025 08:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749716267; cv=none; b=MxqnFRG+o2J8OaMaLlz76KmYdMaL7UCWbLkta1AelV+55ZOQnG3ipBy61RNd3tli/L99K1jX5nA7HKFTs1Rv1QE2vcffr2mpe8B/ipzFc196Nnwnw9P9C+ygURnJciweeIS9x/OHuh1OMD2i9g5W8Mkh1ZivP/PMI0/Bwt/ksRA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749716267; c=relaxed/simple; bh=6LPy8p3Y+iUc3nCkDhjgrYNBYaIU9bUllH3YQM3T+tQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=q+jQYe8dvVBnbj19fe4lqngGb9tkVk/hfiJkDJmqnAOxud+fQJ/BC5ejFFSwGuNCK1LKlE/e8Wx30LlEwG92hTgCYHWX877YEHTmRggMYEsDrPgTaK2YQdA/Gnedply/yIDEkHOnKO/iuqa/IansQbdc6gaXaDJFY8N4hHttgaQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lkOTsJzf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lkOTsJzf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E380AC4CEEA; Thu, 12 Jun 2025 08:17:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749716266; bh=6LPy8p3Y+iUc3nCkDhjgrYNBYaIU9bUllH3YQM3T+tQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lkOTsJzfXKFHp1ZUHQMlqTHjTYpYDytqifyK0eUCzag8Hmc95o6S89pxFNIIupYGq cuep+kRQ/PUphaNcNjVWdy0wNmY8olLrnTceb879AKgqjB+2nX+suKuzF2/T3TK0p0 7+kYs2j8K24Jl5S9Mc1WPDG98oVGiliAKQOJGKeQg+y7I8XU9AkKDzQ3fABhni/e4/ o5ktc8gGOdO17/hmiXZnSsFWAmiHLzAmjPqS5cJX5gU6zrc51DWhlGWWCdHHdubOVZ 3tR4Rl0YmrO2m86hsQAPBZjCKYSmrlatMIpRojxSmpxiOcLCy5jUfinoZEB8Vn/2Ml +JX51oE/0Kl9w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uPd83-006A0a-HM; Thu, 12 Jun 2025 09:17:43 +0100 Date: Thu, 12 Jun 2025 09:17:43 +0100 Message-ID: <86wm9hcr14.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Rutland , Ada Couprie Diaz , Oliver Upton , Joey Gouly , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org Subject: Re: [PATCH V4 1/2] arm64/debug: Drop redundant DBG_MDSCR_* macros In-Reply-To: <20250612033547.480952-2-anshuman.khandual@arm.com> References: <20250612033547.480952-1-anshuman.khandual@arm.com> <20250612033547.480952-2-anshuman.khandual@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, ada.coupriediaz@arm.com, oliver.upton@linux.dev, joey.gouly@arm.com, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 12 Jun 2025 04:35:46 +0100, Anshuman Khandual wrote: >=20 > MDSCR_EL1 has already been defined in tools sysreg format and hence can be > used in all debug monitor related call paths. But using generated sysreg > definitions causes build warnings because there is a mismatch between mds= cr > variable (u32) and GENMASK() based masks (long unsigned int). Convert all > variables handling MDSCR_EL1 register as u64 which also reflects its true > width as well. >=20 > -------------------------------------------------------------------------- > arch/arm64/kernel/debug-monitors.c: In function =E2=80=98disable_debug_mo= nitors=E2=80=99: > arch/arm64/kernel/debug-monitors.c:108:13: warning: conversion from =E2= =80=98long > unsigned int=E2=80=99 to =E2=80=98u32=E2=80=99 {aka =E2=80=98unsigned int= =E2=80=99} changes value from > =E2=80=9818446744073709518847=E2=80=99 to =E2=80=984294934527=E2=80=99 [-= Woverflow] > 108 | disable =3D ~MDSCR_EL1_MDE; > | ^ > -------------------------------------------------------------------------- >=20 > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Rutland > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Reviewed-by: Ada Couprie Diaz > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/assembler.h | 4 ++-- > arch/arm64/include/asm/debug-monitors.h | 6 ------ > arch/arm64/kernel/debug-monitors.c | 22 +++++++++++----------- > arch/arm64/kernel/entry-common.c | 4 ++-- > 4 files changed, 15 insertions(+), 21 deletions(-) >=20 > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/= assembler.h > index ad63457a05c5..f229d96616e5 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -53,7 +53,7 @@ > .macro disable_step_tsk, flgs, tmp > tbz \flgs, #TIF_SINGLESTEP, 9990f > mrs \tmp, mdscr_el1 > - bic \tmp, \tmp, #DBG_MDSCR_SS > + bic \tmp, \tmp, #MDSCR_EL1_SS > msr mdscr_el1, \tmp > isb // Take effect before a subsequent clear of DAIF.D > 9990: > @@ -63,7 +63,7 @@ > .macro enable_step_tsk, flgs, tmp > tbz \flgs, #TIF_SINGLESTEP, 9990f > mrs \tmp, mdscr_el1 > - orr \tmp, \tmp, #DBG_MDSCR_SS > + orr \tmp, \tmp, #MDSCR_EL1_SS > msr mdscr_el1, \tmp > 9990: > .endm > diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include= /asm/debug-monitors.h > index 8f6ba31b8658..1f37dd01482b 100644 > --- a/arch/arm64/include/asm/debug-monitors.h > +++ b/arch/arm64/include/asm/debug-monitors.h > @@ -13,14 +13,8 @@ > #include > =20 > /* Low-level stepping controls. */ > -#define DBG_MDSCR_SS (1 << 0) > #define DBG_SPSR_SS (1 << 21) > =20 > -/* MDSCR_EL1 enabling bits */ > -#define DBG_MDSCR_KDE (1 << 13) > -#define DBG_MDSCR_MDE (1 << 15) > -#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) > - > #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) > =20 > /* AArch64 */ > diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug= -monitors.c > index 58f047de3e1c..08f1d02507cd 100644 > --- a/arch/arm64/kernel/debug-monitors.c > +++ b/arch/arm64/kernel/debug-monitors.c > @@ -34,7 +34,7 @@ u8 debug_monitors_arch(void) > /* > * MDSCR access routines. > */ > -static void mdscr_write(u32 mdscr) > +static void mdscr_write(u64 mdscr) > { > unsigned long flags; > flags =3D local_daif_save(); > @@ -43,7 +43,7 @@ static void mdscr_write(u32 mdscr) > } > NOKPROBE_SYMBOL(mdscr_write); > =20 > -static u32 mdscr_read(void) > +static u64 mdscr_read(void) > { > return read_sysreg(mdscr_el1); > } > @@ -79,16 +79,16 @@ static DEFINE_PER_CPU(int, kde_ref_count); > =20 > void enable_debug_monitors(enum dbg_active_el el) > { > - u32 mdscr, enable =3D 0; > + u64 mdscr, enable =3D 0; > =20 > WARN_ON(preemptible()); > =20 > if (this_cpu_inc_return(mde_ref_count) =3D=3D 1) > - enable =3D DBG_MDSCR_MDE; > + enable =3D MDSCR_EL1_MDE; > =20 > if (el =3D=3D DBG_ACTIVE_EL1 && > this_cpu_inc_return(kde_ref_count) =3D=3D 1) > - enable |=3D DBG_MDSCR_KDE; > + enable |=3D MDSCR_EL1_KDE; > =20 > if (enable && debug_enabled) { > mdscr =3D mdscr_read(); > @@ -100,16 +100,16 @@ NOKPROBE_SYMBOL(enable_debug_monitors); > =20 > void disable_debug_monitors(enum dbg_active_el el) > { > - u32 mdscr, disable =3D 0; > + u64 mdscr, disable =3D 0; > =20 > WARN_ON(preemptible()); > =20 > if (this_cpu_dec_return(mde_ref_count) =3D=3D 0) > - disable =3D ~DBG_MDSCR_MDE; > + disable =3D ~MDSCR_EL1_MDE; > =20 > if (el =3D=3D DBG_ACTIVE_EL1 && > this_cpu_dec_return(kde_ref_count) =3D=3D 0) > - disable &=3D ~DBG_MDSCR_KDE; > + disable &=3D ~MDSCR_EL1_KDE; > =20 > if (disable) { > mdscr =3D mdscr_read(); > @@ -415,7 +415,7 @@ void kernel_enable_single_step(struct pt_regs *regs) > { > WARN_ON(!irqs_disabled()); > set_regs_spsr_ss(regs); > - mdscr_write(mdscr_read() | DBG_MDSCR_SS); > + mdscr_write(mdscr_read() | MDSCR_EL1_SS); > enable_debug_monitors(DBG_ACTIVE_EL1); > } > NOKPROBE_SYMBOL(kernel_enable_single_step); > @@ -423,7 +423,7 @@ NOKPROBE_SYMBOL(kernel_enable_single_step); > void kernel_disable_single_step(void) > { > WARN_ON(!irqs_disabled()); > - mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); > + mdscr_write(mdscr_read() & ~MDSCR_EL1_SS); > disable_debug_monitors(DBG_ACTIVE_EL1); > } > NOKPROBE_SYMBOL(kernel_disable_single_step); > @@ -431,7 +431,7 @@ NOKPROBE_SYMBOL(kernel_disable_single_step); > int kernel_active_single_step(void) > { > WARN_ON(!irqs_disabled()); > - return mdscr_read() & DBG_MDSCR_SS; > + return mdscr_read() & MDSCR_EL1_SS; > } > NOKPROBE_SYMBOL(kernel_active_single_step); > =20 > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-c= ommon.c > index 7c1970b341b8..171f93f2494b 100644 > --- a/arch/arm64/kernel/entry-common.c > +++ b/arch/arm64/kernel/entry-common.c > @@ -344,7 +344,7 @@ static DEFINE_PER_CPU(int, __in_cortex_a76_erratum_14= 63225_wa); > =20 > static void cortex_a76_erratum_1463225_svc_handler(void) > { > - u32 reg, val; > + u64 reg, val; > =20 > if (!unlikely(test_thread_flag(TIF_SINGLESTEP))) > return; > @@ -354,7 +354,7 @@ static void cortex_a76_erratum_1463225_svc_handler(vo= id) > =20 > __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1); > reg =3D read_sysreg(mdscr_el1); > - val =3D reg | DBG_MDSCR_SS | DBG_MDSCR_KDE; > + val =3D reg | MDSCR_EL1_SS | MDSCR_EL1_KDE; > write_sysreg(val, mdscr_el1); > asm volatile("msr daifclr, #8"); > isb(); Whilst you're at it, please also change the open-coded constant in __cpu_setup to MDSCR_EL1_TDCC. Thanks, M. --=20 Without deviation from the norm, progress is not possible.