From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB1DC2F691A for ; Tue, 28 Oct 2025 10:51:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761648702; cv=none; b=lniyfmkwumjUffPvkzUyHJeAiWBsBrC0Ip4jmF9/snFsWh0ouYiprvpJ311/ifXMYOsRrvWgx3csZZyGuqGT/62sYj3R3JZtY/bqMYeTt+thUirR0FTF0UEv6/YRRCkihzNxX1OUAoVtOiz4FYN991NFPAVMP1Ef3muzT0h+pik= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761648702; c=relaxed/simple; bh=Pbgo/x92Vlpm9S0u6S/Gtfa49I9rN6zl/RUeL2NGYyA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=F6NuCB6t0+LkACDjQ6Ks28b7OzTU/1rbyBRjqkC+fIVPV8jbO0jqrP+RlS5SzlFzP/G1wLUgPZnN2O9grMHViMYJNCXwdFMuaq+Oo/UVQ899w6hK0RFO26jgcSIeP2XxsmcpRwG4XvtZpBAMoF8nDwmetRx6xzJILnUR2FBd8ZE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ltQpxj9A; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ltQpxj9A" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3C010C4CEE7; Tue, 28 Oct 2025 10:51:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761648702; bh=Pbgo/x92Vlpm9S0u6S/Gtfa49I9rN6zl/RUeL2NGYyA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ltQpxj9AqC0KGjK0nTSEsd+12Y/yu6tZKpgx6ueqTXbPDqyGkfWse3qeykciOhtxu I2+kbicPfJkH6Ke+SK1vVQVxfqmhwAZebgPjZtITXbFPurD4QB5O3AKDl8wrEVwcrX FEMx3BrKXz8f5IUFbPdhQWSOWwszMconCjlJ47jpcc2D3Dn7LPTpeh6KApwZjVQo3A xvl3JpliD5qVIkDK/qYCoCVbljGpChS7ga3OXpxV7aG8YJVieFq/mBchffBs81BVrb 4xtl3/zSzkhnqU+WKlc70EG2IP3VgispGyXeOVEjkDGC8QFzuMUWI/6W7Vhoc56cl4 K9FkGbaMU4BOA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vDhIh-00000000E7N-46gY; Tue, 28 Oct 2025 10:51:40 +0000 Date: Tue, 28 Oct 2025 10:51:39 +0000 Message-ID: <86y0ovuwn8.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com Subject: Re: [PATCH v1 2/4] KVM: arm64: Add compile-time type check for register in __vcpu_assign_sys_reg() In-Reply-To: <20251027113943.1282568-3-tabba@google.com> References: <20251027113943.1282568-1-tabba@google.com> <20251027113943.1282568-3-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 27 Oct 2025 11:39:41 +0000, Fuad Tabba wrote: > > The 'r' (register) and 'val' (value) parameters in > __vcpu_assign_sys_reg() can be easily transposed. The register ID is an > enum, whereas the value is a u64. This has led to bugs in the past, and > the risk was increased by the historically inconsistent parameter > ordering of the vcpu_write_sys_reg() function. > > To prevent this class of bugs, add a compile-time type compatibility check > to prevent the 'r' parameter from having a 'u64' type. > > This directly catches the erroneous transposition (passing the 'u64' > value as 'r') while remaining flexible, as it does not force 'r' to > be a specific enum type. I don't think that's enough. It is too easy to pass a u32 and accidentally bypass this check. I really think we should redefine the register identifiers to be a fixed value structure, something like this: diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 7501a2ee4dd44..18f65dbff2379 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -624,6 +624,12 @@ enum vcpu_sysreg { NR_SYS_REGS /* Nothing after this line! */ }; +struct vcpu_sys_reg { + enum vcpu_sysreg reg; +}; + +static const struct vcpu_sys_reg vcpu_sys_reg_SCTLR_EL1 = { SCTLR_EL1 }; + struct kvm_sysreg_masks { struct { u64 res0; and then enforce that whatever is interpreted as a system register is actually one of these structures (with some creative cpp wrapping to make it less awkward). In a way, this is similar to what we are doing for page table manipulation, where pte_t is a structure wrapping a u64. If we move to such construct, it becomes impossible to swap value and register, and we can stop worrying about that. Thoughts? M. -- Without deviation from the norm, progress is not possible.