From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92F3F34CD4 for ; Tue, 16 May 2023 16:44:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 35081C433D2; Tue, 16 May 2023 16:44:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684255496; bh=SG7I4zS7JIJvG4Y0yfZXcUEGygr1MHWzVCfVLJnAowM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=aVO8xATRIHNhpp0zVqrm9ump3FzoNzKwCM/j2NrAIks/itRaF1bAXfOER1L4Qrz2/ 3zYJ3jsIVTG3hCDswQ3sEzOvv9Vzwf0sf5ZgE8lUdafuWg0bNiRw26ElB2dI7Fheuo 0Hlsh+sp2czFQoV2CVKGICvQROXvmCDLKSgYi9gVKE7dDC2gAqO90KI9KWHcy231BJ 3D6FftqQWdF92cxihTEuglVPZ+GS+cNW78eBZQwBVPNFox/gi5S0591g87UvqzaYjK AeY9Vz2KIesosmo6OEUKqGvOtYWFxzvKQyau6iAv3eaoEZugjsHyePIk7v4xc88KVl BCVm7XSOC54Fg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pyxnB-00FcCm-SE; Tue, 16 May 2023 17:44:53 +0100 Date: Tue, 16 May 2023 17:44:53 +0100 Message-ID: <86zg64kyyi.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: Cornelia Huck , Shameerali Kolothum Thodi , Jing Zhang , KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta Subject: Re: [PATCH v8 0/6] Support writable CPU ID registers from userspace In-Reply-To: References: <20230503171618.2020461-1-jingzhangos@google.com> <2ef9208dabe44f5db445a1061a0d5918@huawei.com> <868rdomtfo.wl-maz@kernel.org> <1a96a72e87684e2fb3f8c77e32516d04@huawei.com> <87cz30h4nx.fsf@redhat.com> <867ct8mnel.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, cohuck@redhat.com, shameerali.kolothum.thodi@huawei.com, jingzhangos@google.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oupton@google.com, will@kernel.org, pbonzini@redhat.com, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, tabba@google.com, reijiw@google.com, rananta@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 16 May 2023 17:31:29 +0100, Oliver Upton wrote: > > On Tue, May 16, 2023 at 02:11:30PM +0100, Marc Zyngier wrote: > > On Tue, 16 May 2023 12:55:14 +0100, > > Cornelia Huck wrote: > > > > > > Do you have more concrete ideas for QEMU CPU models already? Asking > > > because I wanted to talk about this at KVM Forum, so collecting what > > > others would like to do seems like a good idea :) > > > > I'm not being asked, but I'll share my thoughts anyway! ;-) > > > > I don't think CPU models are necessarily the most important thing. > > Specially when you look at the diversity of the ecosystem (and even > > the same CPU can be configured in different ways at integration > > time). Case in point, Neoverse N1 which can have its I/D caches made > > coherent or not. And the guest really wants to know which one it is > > (you can only lie in one direction). > > > > But being able to control the feature set exposed to the guest from > > userspace is a huge benefit in terms of migration. > > > > Now, this is only half of the problem (and we're back to the CPU > > model): most of these CPUs have various degrees of brokenness. Most of > > the workarounds have to be implemented by the guest, and are keyed on > > the MIDR values. So somehow, you need to be able to expose *all* the > > possible MIDR values that a guest can observe in its lifetime. > > > > I have a vague prototype for that that I'd need to dust off and > > finish, because that's also needed for this very silly construct > > called big-little... > > And the third half of the problem is all of the other IP bits that get > strung together into an SOC :) Errata that live beyond the CPU can > become guest-visible (interconnect for example) and that becomes a bit > difficult to express to the guest OS. So, beyond something like a > big-little VM where the rest of the IP should be shared, I'm a bit > fearful of migrating a VM cross-system. Indeed. But there isn't much we can do about that, and it should be clear to anyone who's remotely involved in this crap that migration to different systems is risky business. > But hey, userspace is in the drivers seat and it can do as it pleases. Exactly. We just need to give it enough of the proverbial rope... > Hopefully we wouldn't need a KVM-specific PV interface for MIDR > enumeration. Perhaps the errata management spec could be expanded to > describe a set of CPU implementations and associated errata... Hence finally making it clear the big-little is a large scale, industry wide erratum? Sign me up! :D More seriously, I'd expect this to be an ARM spec. But it wouldn't hurt having a prototype that serves as a draft for the spec. Better doing that than leaving it to... someone else. Thanks, M. -- Without deviation from the norm, progress is not possible.