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From: Cornelia Huck <cohuck@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: eric.auger.pro@gmail.com, eric.auger@redhat.com,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	kvmarm@lists.linux.dev, richard.henderson@linaro.org,
	alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev,
	sebott@redhat.com, shameerali.kolothum.thodi@huawei.com,
	armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,
	jdenemar@redhat.com, agraf@csgraf.de, shahuang@redhat.com,
	mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com
Subject: Re: [PATCH v7 13/14] arm/cpu: switch to a generated cpu-sysregs.h.inc
Date: Thu, 12 Jun 2025 18:07:40 +0200	[thread overview]
Message-ID: <871prp9c4z.fsf@redhat.com> (raw)
In-Reply-To: <CAFEAcA_Ju4QBUwiOyt9thPxuAFMcm6jVTZHpE8FFJeed5cJgsg@mail.gmail.com>

On Thu, Jun 12 2025, Peter Maydell <peter.maydell@linaro.org> wrote:

> On Thu, 15 May 2025 at 16:40, Cornelia Huck <cohuck@redhat.com> wrote:
>>
>> Generated against Linux 6.14-rc1.
>>
>> Reviewed-by: Sebastian Ott <sebott@redhat.com>
>> Reviewed-by: Eric Auger <eric.auger@redhat.com>
>> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
>> ---
>
> Does it make sense to include all these extra registers?
> Some of them are not simple ID registers at all,
> for example ID_CCSIDR_EL1 is an array of registers, not
> a single value (in QEMU, stored in cpu->ccsidr[]),
> and CSSELR_EL1 is not an ID register at all, it's a
> normal read/write sysreg.

Oops, I think the generator needs to check for op1=={0,1,3} instead of
including op1==2...

[Another issue that came up in recent discussions for the cpu model
series is that recent kernels have made {MIDR,REVIDR,AIDR}_EL1 writable,
but even though they are in the range the kernel reports writable
registers in, the source sysreg file does not include them. I've changed
the script to add them manually so far, but not sure if that is the
best solution here.]


  reply	other threads:[~2025-06-12 16:07 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-15 15:38 [PATCH v7 00/14] arm: rework id register storage Cornelia Huck
2025-05-15 15:38 ` [PATCH v7 01/14] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
2025-05-15 15:38 ` [PATCH v7 02/14] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Cornelia Huck
2025-06-12 15:04   ` Peter Maydell
2025-06-12 15:34     ` Cornelia Huck
2025-06-12 15:39       ` Peter Maydell
2025-05-15 15:38 ` [PATCH v7 03/14] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
2025-05-15 15:38 ` [PATCH v7 04/14] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
2025-05-15 15:38 ` [PATCH v7 05/14] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
2025-05-15 15:38 ` [PATCH v7 06/14] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
2025-05-15 15:39 ` [PATCH v7 07/14] arm/cpu: Store aa64smfr0 " Cornelia Huck
2025-05-15 15:39 ` [PATCH v7 08/14] arm/cpu: Store id_isar0-7 " Cornelia Huck
2025-06-12 15:16   ` Peter Maydell
2025-06-12 15:36     ` Cornelia Huck
2025-06-12 15:39       ` Peter Maydell
2025-06-12 15:53         ` Cornelia Huck
2025-05-15 15:39 ` [PATCH v7 09/14] arm/cpu: Store id_pfr0/1/2 " Cornelia Huck
2025-05-15 15:39 ` [PATCH v7 10/14] arm/cpu: Store id_dfr0/1 " Cornelia Huck
2025-05-15 15:39 ` [PATCH v7 11/14] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
2025-05-15 15:39 ` [PATCH v7 12/14] arm/cpu: Add sysreg generation scripts Cornelia Huck
2025-06-12 15:29   ` Peter Maydell
2025-06-12 15:42     ` Cornelia Huck
2025-05-15 15:39 ` [PATCH v7 13/14] arm/cpu: switch to a generated cpu-sysregs.h.inc Cornelia Huck
2025-06-12 15:35   ` Peter Maydell
2025-06-12 16:07     ` Cornelia Huck [this message]
2025-05-15 15:39 ` [PATCH v7 14/14] arm/kvm: use fd instead of fdarray[2] Cornelia Huck
2025-06-06  9:53 ` [PATCH v7 00/14] arm: rework id register storage Cornelia Huck
2025-06-12 15:36   ` Peter Maydell

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