From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6F3FEA0 for ; Sat, 3 Jun 2023 08:28:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9169DC433EF; Sat, 3 Jun 2023 08:28:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685780917; bh=IOH6BDtjdHdj2Ki7Qz9IKgk5ZqvOjp0LEXK8sZ8Oj/M=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=AqibLvnDTSdlltYZ76xopNcV9SGEyFAqKBJKY16SvdI/KZVj7tBcHz4znHSXtv3vV 2DfdbMkiu/b8C+NZEzx1sGFqkuqQXpIN29Qeek+xcS5ikA/E683px4GhYivLIHyWn+ M9QcoVn1gAKgBtFMZ5Pi3j1055dgh79mJLhXMB7SJEN2A+SD2wqSfjXqKGWq9krvyP +/0Cj2jz0eyLX6H98AhIuOg6eX9uaLHLcMf4M/0uX2aANUT9Kbso/rtQk73l+kuRWW oqVEvbSJjlFLdTFpMZsG6ElEOT3WNxLft7fPrMdcU//hszoKNBSzy00bzbdy9wgyXx SCsOVKLW+7khg== Received: from [37.166.197.171] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1q5Mcl-002Wla-25; Sat, 03 Jun 2023 09:28:35 +0100 Date: Sat, 03 Jun 2023 09:28:33 +0100 Message-ID: <873539ospa.wl-maz@kernel.org> From: Marc Zyngier To: Suraj Jitindar Singh Cc: , , , , , , , , , , , , , Subject: Re: [PATCH 3/3] KVM: arm64: Use per guest ID register for ID_AA64PFR1_EL1.MTE In-Reply-To: <20230602221447.1809849-4-surajjs@amazon.com> References: <20230602005118.2899664-1-jingzhangos@google.com> <20230602221447.1809849-1-surajjs@amazon.com> <20230602221447.1809849-4-surajjs@amazon.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 37.166.197.171 X-SA-Exim-Rcpt-To: surajjs@amazon.com, jingzhangos@google.com, alexandru.elisei@arm.com, james.morse@arm.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oupton@google.com, pbonzini@redhat.com, rananta@google.com, reijiw@google.com, suzuki.poulose@arm.com, tabba@google.com, will@kernel.org, sjitindarsingh@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 02 Jun 2023 23:14:47 +0100, Suraj Jitindar Singh wrote: > > With per guest ID registers, MTE settings from userspace can be stored in > its corresponding ID register. > > No functional change intended. > > Signed-off-by: Suraj Jitindar Singh > --- > arch/arm64/include/asm/kvm_host.h | 21 ++++++++++----------- > arch/arm64/kvm/arm.c | 11 ++++++++++- > arch/arm64/kvm/sys_regs.c | 5 +++++ > 3 files changed, 25 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 7b0f43373dbe..861997a14ba1 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -226,9 +226,7 @@ struct kvm_arch { > */ > #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 > /* Memory Tagging Extension enabled for the guest */ > -#define KVM_ARCH_FLAG_MTE_ENABLED 1 > - /* At least one vCPU has ran in the VM */ > -#define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 > +#define KVM_ARCH_FLAG_HAS_RAN_ONCE 1 > /* > * The following two bits are used to indicate the guest's EL1 > * register width configuration. A value of KVM_ARCH_FLAG_EL1_32BIT > @@ -236,22 +234,22 @@ struct kvm_arch { > * Otherwise, the guest's EL1 register width has not yet been > * determined yet. > */ > -#define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 3 > -#define KVM_ARCH_FLAG_EL1_32BIT 4 > +#define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 2 > +#define KVM_ARCH_FLAG_EL1_32BIT 3 > /* PSCI SYSTEM_SUSPEND enabled for the guest */ > -#define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5 > +#define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 > /* VM counter offset */ > -#define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 6 > +#define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 > /* Timer PPIs made immutable */ > -#define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 7 > +#define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 > /* SMCCC filter initialized for the VM */ > -#define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 8 > +#define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 7 > /* > * AA64DFR0_EL1.PMUver was set as ID_AA64DFR0_EL1_PMUVer_IMP_DEF > * or DFR0_EL1.PerfMon was set as ID_DFR0_EL1_PerfMon_IMPDEF from > * userspace for VCPUs without PMU. > */ > -#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 9 > +#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 8 > > unsigned long flags; > > @@ -1112,7 +1110,8 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); > > #define kvm_has_mte(kvm) \ > (system_supports_mte() && \ > - test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) > + FIELD_GET(ID_AA64PFR1_EL1_MTE_MASK, \ > + IDREG(kvm, SYS_ID_AA64PFR1_EL1))) > > #define kvm_supports_32bit_el0() \ > (system_supports_32bit_el0() && \ > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index ca18c09ccf82..6fc4190559d1 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -80,8 +80,17 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, > if (!system_supports_mte() || kvm->created_vcpus) { > r = -EINVAL; > } else { > + u64 val; > + > + /* Protects the idregs against modification */ > + mutex_lock(&kvm->arch.config_lock); > + > + val = IDREG(kvm, SYS_ID_AA64PFR1_EL1); > + val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_MASK, 1); The architecture specifies 3 versions of MTE in the published ARM ARM, with a 4th coming up as part of the 2022 extensions. Why are you actively crippling the MTE version presented to the guest, and potentially introduce unexpected behaviours? > + IDREG(kvm, SYS_ID_AA64PFR1_EL1) = val; > + > + mutex_unlock(&kvm->arch.config_lock); > r = 0; > - set_bit(KVM_ARCH_FLAG_MTE_ENABLED, &kvm->arch.flags); > } > mutex_unlock(&kvm->lock); > break; > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 59f8adda47fa..8cffb82dd10d 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -3672,6 +3672,11 @@ void kvm_arm_init_id_regs(struct kvm *kvm) > idreg++; > id = reg_to_encoding(idreg); > } > + > + /* MTE disabled by default even when supported */ > + val = IDREG(kvm, SYS_ID_AA64PFR1_EL1); > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); > + IDREG(kvm, SYS_ID_AA64PFR1_EL1) = val; > } > > int __init kvm_sys_reg_table_init(void) Overall, I don't really see the point of such a change. It creates more problems than it solves. Thanks, M. -- Without deviation from the norm, progress is not possible.