From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2AA9C433F5 for ; Thu, 27 Jan 2022 11:08:27 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 2D26E49F5B; Thu, 27 Jan 2022 06:08:27 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@kernel.org Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1SS4+EU8LLZa; Thu, 27 Jan 2022 06:08:25 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E6CF149F07; Thu, 27 Jan 2022 06:08:25 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 735D049F02 for ; Thu, 27 Jan 2022 06:08:24 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E5NWsu8GvzL8 for ; Thu, 27 Jan 2022 06:08:23 -0500 (EST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 2A6BA49F00 for ; Thu, 27 Jan 2022 06:08:23 -0500 (EST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id DE242B821EE; Thu, 27 Jan 2022 11:08:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ABCC0C340E4; Thu, 27 Jan 2022 11:08:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643281700; bh=AP8HPBckMHpuur+KWsdHskLCCjMEybkEiGTwDnOGq70=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=vF0FTfmcqCWaK5clS9XaDpUUU+rj++j+oBVuTaLWOuYWH+VOOEWaheY9veepj6gvZ EvHtGn9qtRYgmBD/mwFaacRQ7h1QKsz/CoozlszgEZNAxyEez4whcbPJP43nsQgJvP 9s68hHFO5FdyDDQ2vx/bpd4B3gWcxiVaDhT9/WcLUaEsIWvwKCOUDEo2w36mv1gEoG IMGk2ffOaC17fVuw3oV2xDgJ24+bkCe3FfaHvkzQayDNM4B82WQCfjgWx9Gv24saI3 bcf6Srpvy5m0mPp8w8RFuwIcVPPmg6PGfr7qiWnJ1T2fgY/BtuXXyf4CSIvIVe3ken KRiU0TrL1Pebw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nD2dW-003Tiy-4l; Thu, 27 Jan 2022 11:08:18 +0000 Date: Thu, 27 Jan 2022 11:08:17 +0000 Message-ID: <874k5p77xa.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Subject: Re: [PATCH v5 14/69] KVM: arm64: nv: Support virtual EL2 exceptions In-Reply-To: References: <20211129200150.351436-1-maz@kernel.org> <20211129200150.351436-15-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, andre.przywara@arm.com, christoffer.dall@arm.com, jintack@cs.columbia.edu, haibo.xu@linaro.org, gankulkarni@os.amperecomputing.com, james.morse@arm.com, suzuki.poulose@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , kvmarm@lists.cs.columbia.edu, Ganapatrao Kulkarni , kernel-team@android.com, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, 20 Jan 2022 13:58:02 +0000, Alexandru Elisei wrote: > > Hi Marc, > > On Mon, Nov 29, 2021 at 08:00:55PM +0000, Marc Zyngier wrote: > > +void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu) > > +{ > > + u64 spsr, elr, mode; > > + bool direct_eret; > > + > > + /* > > + * Going through the whole put/load motions is a waste of time > > + * if this is a VHE guest hypervisor returning to its own > > + * userspace, or the hypervisor performing a local exception > > + * return. No need to save/restore registers, no need to > > + * switch S2 MMU. Just do the canonical ERET. > > + */ > > + spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2); > > + mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT); > > + > > + direct_eret = (mode == PSR_MODE_EL0t && > > + vcpu_el2_e2h_is_set(vcpu) && > > + vcpu_el2_tge_is_set(vcpu)); > > + direct_eret |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t); > > + > > + if (direct_eret) { > > + *vcpu_pc(vcpu) = vcpu_read_sys_reg(vcpu, ELR_EL2); > > + *vcpu_cpsr(vcpu) = spsr; > > + trace_kvm_nested_eret(vcpu, *vcpu_pc(vcpu), spsr); > > + return; > > + } > > + > > + preempt_disable(); > > + kvm_arch_vcpu_put(vcpu); > > + > > + elr = __vcpu_sys_reg(vcpu, ELR_EL2); > > + > > + trace_kvm_nested_eret(vcpu, elr, spsr); > > + > > + /* > > + * Note that the current exception level is always the virtual EL2, > > + * since we set HCR_EL2.NV bit only when entering the virtual EL2. > > + */ > > + *vcpu_pc(vcpu) = elr; > > + *vcpu_cpsr(vcpu) = spsr; > > + > > + kvm_arch_vcpu_load(vcpu, smp_processor_id()); > > + preempt_enable(); > > According to ARM DDI 0487G.a, page D13-3289, ERET'ing to EL1 when > HCR_EL2.TGE is set is an illegal exception return. I don't see this > case treated here. Yes, good call. I've now added handling for both the return to EL1 with TGE set as well as return to a 32bit mode. The return to EL3 case will directly be handled by the HW, and the return from AArch32 to AArch64 cannot happen by construction. Thanks for spotting it. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm