From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oliver.upton@linux.dev>
Cc: kvmarm@lists.linux.dev, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v2 18/27] KVM: arm64: nv: Handle effects of HCRX_EL2.TMEA on SError injection
Date: Sat, 21 Jun 2025 14:03:13 +0100 [thread overview]
Message-ID: <87ecvdfdri.wl-maz@kernel.org> (raw)
In-Reply-To: <20250616230308.1192565-19-oliver.upton@linux.dev>
On Tue, 17 Jun 2025 00:02:59 +0100,
Oliver Upton <oliver.upton@linux.dev> wrote:
>
> HCRX_EL2.TMEA further modifies the physical SError behavior where
> unmasked SErrors are taken to EL1 and masked SErrors are taken to EL2.
> This gets a bit hairy when considering the fact that TMEA also enables
> vSErrors, i.e. KVM has delegated the HW vSError context to the guest
> hypervisor.
>
> We can keep the vSError context ownership by taking advantage of a
> couple properties:
>
> - If SErrors are unmasked, the 'physical' SError can be taken
> in-context immediately. In other words, KVM can emulate the EL1
> SError while preserving vEL2's ownership of the vSError context.
>
> - If SErrors are masked, the 'physical' SError is taken to EL2 and
> needs the usual nested exception entry.
>
> Note that the new in-context handling has the benign effect where
> unmasked SError injections are emulated even for non-nested VMs.
This patch isn't *just* about HCRX_EL2.TMEA, right? Clearly,
SCTLR2_ELx.NMEA plays a role. One is about routing, while the other is
about bypassing PSTATE.A (NM stands for Non-Maskable). Also, TMEA
affects both SEA and SError, while NMEA is SError only.
For the sake of making things a bit clearer, it might be worth either
describing the effects of NMEA here, or split the NMEA handling to
another patch.
>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
> arch/arm64/kvm/inject_fault.c | 36 +++++++++++++++++++++++++++++++++--
> 1 file changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
> index cab14a926bc6..e689002f10b6 100644
> --- a/arch/arm64/kvm/inject_fault.c
> +++ b/arch/arm64/kvm/inject_fault.c
> @@ -97,6 +97,11 @@ static bool effective_sctlr2_ease(struct kvm_vcpu *vcpu)
> return __effective_sctlr2_bit(vcpu, SCTLR2_EL1_EASE_SHIFT);
> }
>
> +static bool effective_sctlr2_nmea(struct kvm_vcpu *vcpu)
> +{
> + return __effective_sctlr2_bit(vcpu, SCTLR2_EL1_NMEA_SHIFT);
> +}
> +
> static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
> {
> unsigned long cpsr = *vcpu_cpsr(vcpu);
> @@ -258,14 +263,29 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu)
> inject_undef64(vcpu);
> }
>
> +static bool serror_is_masked(struct kvm_vcpu *vcpu)
> +{
> + bool masked = *vcpu_cpsr(vcpu) & PSR_A_BIT;
> +
> + if (!vcpu_mode_priv(vcpu))
> + masked |= effective_sctlr2_nmea(vcpu);
> +
> + return masked;
> +}
> +
> static bool kvm_serror_target_is_el2(struct kvm_vcpu *vcpu)
> {
> - return is_hyp_ctxt(vcpu) || vcpu_el2_amo_is_set(vcpu);
> + if (is_hyp_ctxt(vcpu) || vcpu_el2_amo_is_set(vcpu))
> + return true;
> +
> + return serror_is_masked(vcpu) &&
> + (__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TMEA);
> }
>
> static bool kvm_serror_undeliverable_at_el2(struct kvm_vcpu *vcpu)
> {
> - return !(vcpu_el2_tge_is_set(vcpu) || vcpu_el2_amo_is_set(vcpu));
> + return !(vcpu_el2_tge_is_set(vcpu) || vcpu_el2_amo_is_set(vcpu) ||
> + effective_sctlr2_nmea(vcpu));
> }
>
> int kvm_inject_serror_esr(struct kvm_vcpu *vcpu, u64 esr)
> @@ -281,6 +301,18 @@ int kvm_inject_serror_esr(struct kvm_vcpu *vcpu, u64 esr)
> return 1;
> }
>
> + /*
> + * Emulate the exception entry if SErrors are unmasked. This is useful if
> + * the vCPU is in a nested context w/ vSErrors enabled then we've already
> + * delegated he hardware vSError context (i.e. HCR_EL2.VSE, VSESR_EL2,
> + * VDISR_EL2) to the guest hypervisor.
> + */
> + if (!serror_is_masked(vcpu)) {
> + pend_serror_exception(vcpu);
> + vcpu_write_sys_reg(vcpu, esr, exception_esr_elx(vcpu));
> + return 1;
> + }
> +
> vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
> *vcpu_hcr(vcpu) |= HCR_VSE;
> return 1;
I see that the handling of TMEA affecting the routing of SEAs is in a
follow-up patch, but it'd be good to either call out the split in the
commit message, or have a single patch addressing all of the TMEA
effects.
None of that affects the code, which seems correct (well, I think -- I
can sense a headache coming!).
Thanks,
M.
--
Jazz isn't dead. It just smells funny.
next prev parent reply other threads:[~2025-06-21 13:03 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-16 23:02 [PATCH v2 00/27] KVM: arm64: SCTLR2, DoubleFault2, and NV external abort fixes Oliver Upton
2025-06-16 23:02 ` [PATCH v2 01/27] arm64: Detect FEAT_SCTLR2 Oliver Upton
2025-06-16 23:02 ` [PATCH v2 02/27] arm64: Detect FEAT_DoubleFault2 Oliver Upton
2025-06-16 23:02 ` [PATCH v2 03/27] KVM: arm64: Add helper to identify a nested context Oliver Upton
2025-06-16 23:02 ` [PATCH v2 04/27] KVM: arm64: Treat vCPU with pending SError as runnable Oliver Upton
2025-06-16 23:02 ` [PATCH v2 05/27] KVM: arm64: nv: Respect exception routing rules for SEAs Oliver Upton
2025-06-21 9:51 ` Marc Zyngier
2025-06-16 23:02 ` [PATCH v2 06/27] KVM: arm64: nv: Honor SError exception routing / masking Oliver Upton
2025-06-21 10:47 ` Marc Zyngier
2025-06-24 11:44 ` Oliver Upton
2025-06-16 23:02 ` [PATCH v2 07/27] KVM: arm64: nv: Add FEAT_RAS vSError sys regs to table Oliver Upton
2025-06-16 23:02 ` [PATCH v2 08/27] KVM: arm64: nv: Use guest hypervisor's vSError state Oliver Upton
2025-06-21 11:09 ` Marc Zyngier
2025-06-16 23:02 ` [PATCH v2 09/27] KVM: arm64: nv: Advertise support for FEAT_RAS Oliver Upton
2025-06-16 23:02 ` [PATCH v2 10/27] KVM: arm64: nv: Describe trap behavior of SCTLR2_EL1 Oliver Upton
2025-06-16 23:02 ` [PATCH v2 11/27] KVM: arm64: Wire up SCTLR2_ELx sysreg descriptors Oliver Upton
2025-06-16 23:02 ` [PATCH v2 12/27] KVM: arm64: Context switch SCTLR2_ELx when advertised to the guest Oliver Upton
2025-06-16 23:02 ` [PATCH v2 13/27] KVM: arm64: Enable SCTLR2 " Oliver Upton
2025-06-16 23:02 ` [PATCH v2 14/27] KVM: arm64: Describe SCTLR2_ELx RESx masks Oliver Upton
2025-06-21 11:34 ` Marc Zyngier
2025-06-16 23:02 ` [PATCH v2 15/27] KVM: arm64: Factor out helper for selecting exception target EL Oliver Upton
2025-06-16 23:02 ` [PATCH v2 16/27] KVM: arm64: nv: Ensure Address size faults affect correct ESR Oliver Upton
2025-06-16 23:02 ` [PATCH v2 17/27] KVM: arm64: Route SEAs to the SError vector when EASE is set Oliver Upton
2025-06-21 11:54 ` Marc Zyngier
2025-06-24 8:12 ` Oliver Upton
2025-06-16 23:02 ` [PATCH v2 18/27] KVM: arm64: nv: Handle effects of HCRX_EL2.TMEA on SError injection Oliver Upton
2025-06-21 13:03 ` Marc Zyngier [this message]
2025-06-16 23:03 ` [PATCH v2 19/27] KVM: arm64: Take "masked" SEAs to EL2 when TMEA is set Oliver Upton
2025-06-22 8:39 ` Marc Zyngier
2025-06-16 23:03 ` [PATCH v2 20/27] KVM: arm64: nv: Enable vSErrors when HCRX_EL2.TMEA " Oliver Upton
2025-06-16 23:03 ` [PATCH v2 21/27] KVM: arm64: Advertise support for FEAT_SCTLR2 Oliver Upton
2025-06-16 23:03 ` [PATCH v2 22/27] KVM: arm64: Advertise support for FEAT_DoubleFault2 Oliver Upton
2025-06-16 23:03 ` [PATCH v2 23/27] KVM: arm64: Don't retire MMIO instruction w/ pending (emulated) SError Oliver Upton
2025-06-16 23:03 ` [PATCH v2 24/27] KVM: arm64: selftests: Add basic SError injection test Oliver Upton
2025-06-16 23:03 ` [PATCH v2 25/27] KVM: arm64: selftests: Test SEAs are taken to SError vector when EASE=1 Oliver Upton
2025-06-16 23:03 ` [PATCH v2 26/27] KVM: arm64: selftests: Add SCTLR2_EL1 to get-reg-list Oliver Upton
2025-06-16 23:03 ` [PATCH v2 27/27] KVM: arm64: selftests: Catch up set_id_regs with the kernel Oliver Upton
2025-06-22 9:25 ` [PATCH v2 00/27] KVM: arm64: SCTLR2, DoubleFault2, and NV external abort fixes Marc Zyngier
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